high-speed architecture for a programmable frequency divider and a dual-modulus prescaler

high-speed architecture for a programmable frequency divider and a dual-modulus prescaler

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时间:2018-02-10

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1、744IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.31,NO.5,MAY1996High-speedArchitectureforaProgrammableFrequencyDividerandaDual-ModulusPrescalerPatrikLarssonAbstract-Wepresentaprescalerarchitecturethatissuitableforhigh-speedCMOSapplications.Weapplythearchitecturetoa4/5andan8/9dual-modulusprescalerandob

2、tainamea-suredmaximumclockfrequencyof1.90GHzinastandard0.8pmCMOShulkprocess.Thisis13%fasterthanthetraditionalprescalerarchitecturekeepingthesamepowerconsumption.Wealsoapplythekeypartoftheprescalertoadivide-by-Ncircuitreaching1.75GHz.ThisisthreetimesfasterthananypreviouslyreportedCMOSimplement

3、ationandcomparabletoGaAsimplementations.I.INTRODUCTION0NEofthehigh-frequencybuildingblocksinacom-Clkmunicationsystemisafrequencysynthesizerinclud-ingafrequencydivider.Traditionally,thedividerhas(b)beenrealizedwithahigh-speedtechnologysuchasbi-Fig.1.Dual-modulus819prescalers.(a)Basedonashiftre

4、gisterring.polarorGaAs.CMOSisthecheapesttechnologytoday(b)Withpreprocessingoftheclocksignal.andseemstobethecheapestalternativefortheforeseenfuture,indicatingthatCMOSimplementationsareadvan-clocksignalandthenusecascadeddivide-by-twostagestageous.assketchedinFig.l(b).TheonedetectorgivesalowTher

5、earethreetypesoffrequencydividers:cascadedoutputpulsewhentheMsignalandtheoutputsofalldi-divide-by-twostages,dual-modulusprescaler,andpro-vide-by-twostagesarehigh.Thispulseisdelayedonegrammabledivider(alsocalleddivide-by-Ncircuit).ManyclockcycleandsynchronizedwiththeinvertedClksignalapplicatio

6、nsrequireaprogrammabledivisionratio,ex-intheDflip-flop.Alowoutputwillprohibitonenegativecludingtheuseofdivide-by-twostages.Inthispaper,wepulseoftheCZksignalfromreachingthefirstdivide-by-presentanovelarchitectureforbothadual-moduluspre-twostage.Aftercancelingoneclockpulse,itwilltakescalerandad

7、ivide-by-Ncircuit.eightclockpulsesbeforethedetectoroutputgoeslow,givingadivisionratioofnine.BysettingMlow,thede-SomeCMOSprescalershavebeenpresented[11-[3]withamaximumoperatingfrequencynotfarbehindbi-tectoroutputisalwayshighandtheprescalerdivi

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