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1、130IEEETRANSACTIONSONCIRCUITSANDSYSTEMS—II:ANALOGANDDIGITALSIGNALPROCESSING,VOL.50,NO.3,MARCH2003TransactionsBriefs__________________________________________________________________ANewFrequencySynthesisMethodBasedon“Flying-Adder”ArchitectureLimingXiuandZhihongYouAbstract—The“flying-adder”frequency
2、andphasesynthesisarchitec-turewaspresentedinpaperspublishedbyMairandXiuin2000andXiuandYouin2002.Thisarchitecturecontainsmanyexcellentfeaturesanditcanbeimplemented/integratedeasilyinaverylargescaleintegrationsystem.However,ithasadrawbackofinherentjitterontheoutputfre-quency,duetothefrequencymodulati
3、onoftheoutputfrequency.ThisbriefFig.1.Blockdiagramofthenewmethod.presentsanewfrequencysynthesismethodthateliminatessuchjitter.Thefrequencyaccuracyofthisnewarchitectureisstudied;subsequently,thefrequencyerrorupperboundisfound.Furthermore,itleadstothedevel-opmentofaschemethatcanbeusedtoderivethefrequ
4、encyerrordistribu-ortion.Thecomparisonto“integer-N”and“fractional-N”phase-lockedloopTFREQ=(2)(PLL)basedfrequencysynthesistechniquesisalsopresented.1IndexTerms—Flying-adder,fractional-Nphase-lockedloop(PLL),fre-whereT=1=fisthedesiredfrequency,1isthetimedifferencequencyaccuracy,frequencysynthesis,int
5、eger-Nphase-lockedloop(PLL).betweentwoadjacentVCOoutputs.FREQisthedigitalcontrolwordforfrequency.Examplescanbefoundin[1].I.INTRODUCTIONC.InherentJitter[1]The“flying-adder”architectureisanewwayoffrequencyandphase1)Peak-to-PeakJitter(delay)synthesis.Comparingtoconventionalfrequencysynthesismethods,th
6、isarchitectureoffersmanyuniquefeaturessuchastheJpk0pk=1(3)flexibilityofchangingoutputfrequencyinstantlywithoutanydynamicprocess,anyfrequencycanbeachievedwithpredestinedaccuracy,2)JitterMeanvariousphase-shiftedandduty-cycleversionsoftheoutputsignalcanbegenerated,theincrementalvaluecanbeeasilymodulat
7、edtoproduceJmean=0(4)ahighlyaccurateandpredictablespreadspectrumclocksource,andetc.Amongthese,themostdistinguishfeatureis“anyfrequencycanbe3)rmsJitterachievedwithpredestinedaccuracy.”Thisisachievedbymodulat