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1、IEEETRANSACTIONSONCIRCUITSANDSYSTEMS—I:REGULARPAPERS,VOL.58,NO.6,JUNE20111225ADCVSLDelayCellforFastLowPowerFrequencySynthesisApplicationsDidemZ.Turker,StudentMember,IEEE,SunilP.Khatri,Member,IEEE,andEdgarSánchez-Sinencio,LifeFellow,IEEEAbstract—Inthispaper,alow-cost,powerefficientandfastTh
2、ekeypower-hungrycircuitsinafrequencysynthesizerareDifferentialCascodeVoltage-Switch-Logic(DCVSL)baseddelaythevoltage-controlledoscillator(VCO)andthefrequencydi-cell(namedDCVSL-R)isproposed.WeusetheDCVSL-Rcellviders[1],especiallytheprogrammabledividersthatoperateattoimplementhighfrequencya
3、ndpower-criticaldelaycellsandflip-flopsofringoscillatorsandfrequencydividers.Whencom-theRFfrequency.AnotherpowerhungryblockistheRFbuffersparedtoTSPC,DCVSLcircuitsoffersmallinputandclockbetweentheVCOandthefrequencydividers.Alongwithfre-capacitanceandasymmetricdifferentialloadingforpreviousqu
4、encyofoperationandtechnologyspeed,thecircuitdesignRFstages.WhencomparedtoCML,theyofferlowtransistortechniqueofthefrequencydividersiskeyindeterminingtheircount,noheadroomlimitation,rail-to-railswingandnostaticandtheirdrivingbuffer’spowerconsumption.Untilrecently,currentconsumption.However,
5、DCVSLcircuitssufferfromalargelow-to-highpropagationdelay,whichlimitstheirspeedCurrentModeLogic(CML)circuits[2],[3]werewidelyem-andresultsinasymmetricaloutputwaveforms.Theproposedployedinthefrequencydividersofsynthesizers[4],[5]be-DCVSL-RcircuitembodiesthebenefitsofDCVSLwhilere-causetheycou
6、ldoperateathighfrequencies.Withthemigra-ducingthetotalpropagationdelay,achievingfasteroperation.tiontowardssub-microntechnologies,digitaldynamic-circuitDCVSL-Ralsogeneratessymmetricaloutputwaveformswhicharecriticalfordifferentialcircuits.AnothercontributionofthistechniquessuchasTrue-Singl
7、e-PhaseClocking(TSPC)arebe-workisaclosed-formdelaymodelthatpredictsthespeedofcomingpopular[6]–[8]tooptimizethepowerconsumptionofDCVSLcircuitswith8%worstcaseaccuracy.Weimplementtwohigh-speedfrequencydividers.ring-oscillator-basedVCOsin0.13mtechnologywithDCVSLInthispa