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1、Circuit-awareDeviceDesignMethodologyforNanometerTechnologies:ACaseStudyforLowPowerSRAMDesignQikaiChen,SaibalMukhopadhyay,AdityaBansalandKaushikRoySchoolofElectricalandComputerEngineering,PurdueUniversity,WestLafayette,IN,USA{qikaichen,sm,bansal,kaushik}@purdue.eduAbstract:thresholdleakage(
2、SBSRAM,BB-SRAM)andtosomeextentthegateInthispaper,weproposeageneralCircuit-awareDeviceleakage(SBSRAM).However,theymayadverselyimpactotherDesignmethodology,whichcanimprovetheoverallcircuitdesignleakagecomponents.Forexample,areverse-body-biasintheSRAMbytakingadvantagesoftheindividualcircuitch
3、aractersduringstand-bymode(RBB-SRAM)actuallyincreasesthejunctionthedevicedesignphase.Theproposedmethodologyanalyticallytunnelingband-to-bandleakage.Since,innano-scaledevices,powerderivestheoptimaldeviceintermsofthepre-specifiedcircuitconsumptionsduetoeachofthethreeleakagecomponentsarequali
4、tyfactor.WeappliedtheproposedmethodologytoSRAMcomparable[4],theeffectivenessofthedifferentcircuittechniquedesignandachievedsignificantreductioninstandbyleakageanddependsconsiderablyontherelativemagnitudesofeachleakageaccesstime(11%and7%,respectively,forconventional6T-componentinadevice.SRA
5、M).Also,weobservedthattheoptimaldevicesselectedConventionallythedesignsolutionshavebeensoughtdependconsiderablyontheappliedcircuittechniques.Webelieveindependentlyfromthedeviceandthecircuitlevels.InthedevicethattheproposedCircuit-awareDeviceDesignmethodologywilllevel,geometryanddopingprofi
6、leofthetransistorsareoptimizedtobeusefulinthesub-90nmtechnology,wheredifferentleakagemaximizethe“ON”current(Ion)whileminimizingthe“OFF”(Ioff)components(subthreshold,gate,andjunctiontunneling)arecurrent(i.e.tomaximizetheIon/Ioffratio).Inthecircuitlevel,comparableinmagnitude.Also,inthiswork,
7、wehavepresentedadifferentlowpowercircuitsolutionsareoptimizedthroughtransistordesignautomationframeworkforSRAM,whichisconventionallysizing,properselectionofsource-biasorbody-biasvoltagesasincustomdesignedandoptimized.SBSRAMorBB-SRAM,andetc.Then,lowpowercircuit