2013EDA实验考试——沈斌

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1、用VHDL设计数字电压表并通过实验箱验证。一、设计任务（功能）1.测量范围0—5V，精度为0.1。2.2位数码管显示且显示小数点。二、设计所用实验仪器（说明编号）1.计算机QuartusII8.0(32-Bit)编号20065925002.EDA试验箱编号2004228200三、设计流程(1).为本工程建立文件夹1031340131打开软件并新建一个设计文件输入所需文件建立底层文件adcint.vhd,disp.vhd,scanselect.vhd和tran.vhd有底层文件画出顶层文件原理图(2).编译文件并仿真锁定引脚(3).连接线路并下载(4).进行硬件测试设

2、计流程的图形与文字简要描述打开QuartusII8.0(32-Bit)新建工程：打开file，点击NewProjectwizard选择根目录文件夹为10031340131建立顶层文件为top点击NEXT考生答题不得过此线··················密······························封························线···························院系信控专业电子信息工程年级10级班级一班　姓名沈斌学号10031340131··················装················

3、··············订························线···························第7页共8页将5个源文件选定并添加选择器件FLEX10K封装PLCC选择EPF10K10LC84-4点击NEXT再次点击NEXT最后点击Finish建好顶层文件点击该按钮进行编译点击file----New选择新建VectorWaveformFile建立仿真波形图考生答题不得过此线··················密······························封························线····

4、·······················院系信控专业电子信息工程年级10级班级一班　姓名沈斌学号10031340131··················装······························订························线···························第7页共8页点击鼠标右键选择Insert—InsertNoderorbus...选择NoderFinder在pins：all中list所有引脚在DesignEntry（allname）中list找current-state1.添加完引脚后在ed

5、it中找到EndTime点击修改时间为100us2.各个信号的输入后面详细介绍仿真信号设定好后，点击File—saveas保存仿真图为top（改名字必须与顶层文件名和工程名一致）点击Assignments中pins进行引脚的锁将各个引脚锁定好考生答题不得过此线··················密······························封························线···························院系信控专业电子信息工程年级10级班级一班　姓名沈斌学号10031340131···············

6、···装······························订························线···························第7页共8页再次编译后在Tools中点击Programmer进行程序的加载点击HardwareSetup选择试验箱后点击Start四、设计原理设计的各模块所实现的功能1.用状态机实现对ADC0809采样控制ADC0809是CMOS的8位A/D转换器，片内有8路模拟开关，可控制8个模拟量中的一个进入转换器中，转换时间约100us，含锁存控制的8路多路开关，输出由三态缓冲器控制，单5v电源供电。(1

7、).生成adcint并建立仿真波形文件(2).输入adcint.vhd文本并保存指向工程编译并仿真结果分析：刚开始EOC为低电平时状态机：St0为开始St1CLK上升沿时WR置高电平将数据锁存St2当EOC一直为低电平时等待转换St3当EOC出现上升沿时的下一个CLK的上升沿RD置高电平0809开始进行转换St0转换结束等待锁存St1当CLK上升沿时WR置高电平将数据锁存St2等待下一个数据的转换当CLK上升沿时跳转到上面的st3依次循环直到EOC出现下降沿转换结束2.4位数码扫描显示电路考生答题不得过此线··················密·········