VHDL源代码-计数器

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1、十五计数器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;ENTITYfiveteencoutISPORT(clk,reset,enable:INstd_logic;count:OUTstd_logic_vector(3downto0));ENDfiveteencout;ARCHITECTUREcounterOFfiveteencoutISSIGNALcount_int:std_logic_vector(0to3);BEGINPROCESS(clk,reset)

2、BEGINWAITUNTILrising_edge(clk);IFreset='1'THENcount_int<=(OTHERS=>'0');ELSIFenable='1'THENIF(count_int="1110")THENcount_int<="0000";ELSEcount_int<=count_int1;--ELSE--NULL;--IF(count_int="1001")THEN--count_int<="0000";ENDIF;ENDIF;ENDPROCESS;count<=count_int;--IF(reset='0')then--q

3、<="0000";---ELSIF(clk'eventandclk='1')THEN--q<=q1;--IF(q<="1001")then--q<="0000";---ENDIF;--IF(reset<='1')THEN--q<="00";--ELSIF--waituntil(clk'eventandclk='1');--WAITUNTIL(clk'EVENTANDclk='1');--WAITUNTIL(clock'EVENTANDclock='1');--q<=q'1';--endif;--count<=q;--WAITUNTILclock='1'

4、;--if(clock'eventandclock='1')then--WAITUNTILrising_edge(clock);--clock'eventandclock='1';--count<=0;--WAITUNTIL(clock'EVENTANDclock='1');--WAITriseedgeclock='1';--if(clock'eventandclock='1')then--WAITUNTILrising_edge(clock);--count<=1;--WAITUNTIL(clock'EVENTANDclock='1');--WAIT

5、UNTILclock='1';--if(clock'eventandclock='1')then--WAITUNTILrising_edge(clock);--count<=2;--endif;--endif;--endif;--ENDPROCESS;ENDcounter;十四计数器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;ENTITYfourteencoutISPORT(clk,reset,enable:INstd_logic;count:OUTstd_

6、logic_vector(3downto0));ENDfourteencout;ARCHITECTUREcounterOFfourteencoutISSIGNALcount_int:std_logic_vector(0to3);BEGINPROCESS(clk,reset)BEGINWAITUNTILrising_edge(clk);IFreset='1'THENcount_int<=(OTHERS=>'0');ELSIFenable='1'THENIF(count_int="1101")THENcount_int<="0000";ELSEcount_

7、int<=count_int1;--ELSE--NULL;--IF(count_int="1001")THEN--count_int<="0000";ENDIF;ENDIF;ENDPROCESS;count<=count_int;--IF(reset='0')then--q<="0000";---ELSIF(clk'eventandclk='1')THEN--q<=q1;--IF(q<="1001")then--q<="0000";---ENDIF;--IF(reset<='1')THEN--q<="00";--ELSIF--waituntil(clk

8、'eventandclk='1');--WAITUNTIL(clk'EVENTANDclk='