60进制计数器VHDL语言

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1、LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYbcd60countISPORT(clk,bcd1wr,bcd10wr,cin:INSTD_LOGIC;co:OUTSTD_LOGIC;datain:INSTD_LOGIC_VECTOR(3DOWNTO0);bcd1:OUTSTD_LOGIC_VECTOR(3DOWNTO0);bcdm:OUTSTD_LOGIC_VECTOR(2DOWNTO0));ENDENTITYBCD60COUNT

2、;ARCHITECTURERTLOFBCD60COUNTISSIGNALBCD1N:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALBCDUN:STD_LOGIC_VECTOR(2DOWNTO0);BEGINBCD1<=bcd1n;bcdm<=BCDUN;PROCESS(CLK,BCD1WR)ISBEGINIF(bcd1wr='1')THENbcd1N<=DATAIN;ELSIF(CLK'EVENTANDclk='1')THENIF(cin='1')THENIF(bcd1n=9)THENbcd1n<="0000";E

3、LSEbcd1n<=bcd1n+1;endif;endif;endif;ENDPROCESS;PROCESS(clk,bcd10wr)ISBEGINIF(bcd10wr='1')THENBCDUN<=datain(2DOWNTO0);ELSIF(clk'EVENTANDclk='1')THENIF(cin='1'ANDbcd1n=9)THENIF(BCDUN=5)THENBCDUN<="000";ELSEBCDUN<=BCDUN+1;ENDIF;endif;ENDIF;ENDPROCESS;PROCESS(BCDUN,bcd1n,ci

4、n)ISBEGINIF(cin='1'ANDbcd1n=9ANDBCDUN=5)THENco<='1';ELSEco<='0';ENDIF;ENDPROCESS;ENDARCHITECTURErtl;