用vhdl语言设计计数器

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1、76进制计数器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCDU_76ISPORT(CLK:INSTD.LOGIC;Q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCDU_76;ARCHITECTUREAAOFCDU_76ISSIGNALCOUT2,COUT1:STD_L0GIC_VECT0R(3DOWNTO0);BEGINPROCESS(CLK)BEGINIF(CLK’EVENTANDC

2、LK二’f)THENIF(COUT2=7ANDCOUT1=5)THENCOUT2<=nOOOOM;COUT1<=H0000n;ELSEIF(COUT1=9)THENCOUT2<=COUT2+1;COUT1<=”0000";ELSECOUT2<=COUT2;COUT1<=COUT1+1;ENDIF;ENDIF;ENDIF;ENDPROCESS;Q<=COUT2&COUT1;ENDAA;24进制计数器NameVftlnpftt13.9us34.38usi54.8,6uS75.34iiIS95.82iis116.

3、3vIS1

4、8.38nsCLKBOaqH00Q3YQ4TqTOQDDCK)QDQlXiDC互2DCoc02Q[0]BO1-11_1~1J_L1~111r-1r-11_1rTQ[l]BOI!1J:L」Q[2]BOlis1LQ[3]BO1'I11Q[4]BO1•三Q[5]BOQ[6]BOQ[T]BOLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCDU_24ISPORT(CLK:INSTD.LOGIC;Q:OUTSTD_L0GIC_

5、VECT0R(7DOWNTO0));ENDCDU_24;ARCHITECTUREAAOFCDU_24ISSIGNALCOUT2,COUT1:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK)BEGINIF(CLK'EVENTANDCLK=’1•)THENIF(COUT2=2ANDCOUT1=3)THENCOUT2<=nOOOO";COUTl<="OOOOn;ELSEIF(COUT1=9)THENCOUT2<=COUT2+1;COUT1<=M0000H;ELSECOUT2<=COUT

6、2;COUT1<=COUT1+1;ENDIF;ENDIF;ENDIF;ENDPROCESS;Q<=COUT2&COUT1;ENDAA;用VHDL设计一个带高电平使能信号、低电平清零信号、低电平罝数信号的十进制计数器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT10ISPORT(CLK,SET,CLR,EN:INSTD_LOGIC;CQ:OUTSTD_L0GIC_VECT0R(3DOWNTO0);COUT:OU

7、TSTDJLOGIC);ENDCNT10;ARCHITECTUREbehavOFCNT10ISBEGINPROCESS(CLK,SET,CLR,EN)VARIABLECQI:STD_L0GIC_VECT0R(3DOWNTO0);BEGINIFCLR=,O,THENCQI:=(OTHERS=〉’0’)；ELSIFCLK'EVENTANDCLK^l*THENIFSET=,O,THENCQI:=(OTHERS=〉T);ELSIFEN^VTHENIFCQI<9THENCQI:=CQI+1;ELSECQI:=(OTHERS=>,

8、0,);ENDIF;ENDIF;ENDIF;IFCQI=9THENCOUTW;ELSECOUWO1;ENDIF;CQ<=CQI;ENDPROCESS;ENDbehav;