用vhdl语言设计计数器.doc

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1、用vhdl语言设计计数器__________________________________________________76进制计数器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCDU_76ISPORT(CLK:INSTD_LOGIC;Q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCDU_76;ARCHITECTUREAAOFCDU_76ISSIGNALCOUT2,COUT1:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCE

2、SS(CLK)BEGINIF(CLK'EVENTANDCLK='1')THENIF(COUT2=7ANDCOUT1=5)THENCOUT2<="0000";COUT1<="0000";____________________________________________________________________________________________________ELSEIF(COUT1=9)THENCOUT2<=COUT2+1;COUT1<="0000";ELSECOUT2<=COUT2;COUT1<=COUT1+1;ENDIF;ENDIF;ENDIF;ENDPRO

3、CESS;Q<=COUT2&COUT1;ENDAA; 24进制计数器LIBRARYIEEE;____________________________________________________________________________________________________USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCDU_24ISPORT(CLK:INSTD_LOGIC;Q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCDU_24;ARCHITECTUREAA

4、OFCDU_24ISSIGNALCOUT2,COUT1:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK)BEGINIF(CLK'EVENTANDCLK='1')THENIF(COUT2=2ANDCOUT1=3)THENCOUT2<="0000";COUT1<="0000";ELSEIF(COUT1=9)THENCOUT2<=COUT2+1;COUT1<="0000";ELSECOUT2<=COUT2;COUT1<=COUT1+1;ENDIF;ENDIF;ENDIF;ENDPROCESS;Q<=COUT2&COUT1;_______________

5、_____________________________________________________________________________________ENDAA;用VHDL设计一个带高电平使能信号、低电平清零信号、低电平置数信号的十进制计数器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT10ISPORT(CLK,SET,CLR,EN:INSTD_LOGIC;CQ:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC

6、);____________________________________________________________________________________________________ENDCNT10;ARCHITECTUREbehavOFCNT10ISBEGINPROCESS(CLK,SET,CLR,EN)VARIABLECQI:STD_LOGIC_VECTOR(3DOWNTO0);BEGINIFCLR='0'THENCQI:=(OTHERS=>'0');ELSIFCLK'EVENTANDCLK='1'THENIFSET='0'THENCQI:=(OTHERS=>

7、'1');ELSIFEN='1'THENIFCQI<9THENCQI:=CQI+1;ELSECQI:=(OTHERS=>'0');ENDIF;ENDIF;ENDIF;IFCQI=9THENCOUT<='1';ELSECOUT<='0';ENDIF;CQ<=CQI;ENDPROCESS;ENDbehav;________________________________________________________________________