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1、3-8译码器的VHDL设计1.实体框图2.程序设计正确的程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDECODER38AISPORT(A2,A1,A0,S1,S2,S3:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYDECODER38A;ARCHITECTUREONEOFDECODER38AISSIGNALS:STD_LOGIC_VECTOR(5DOWNTO0);BEGINS<=A2&A1&A0&S1&S2&S3;WITHSSELECTY<=
2、"11111110"WHEN"000100","11111101"WHEN"001100","11111011"WHEN"010100","11110111"WHEN"011100","11101111"WHEN"100100","11011111"WHEN"101100","10111111"WHEN"110100","01111111"WHEN"111100","11111111"WHENOTHERS;ENDARCHITECTUREONE;3.仿真波形图4.仿真波形分析当S1S2S3=100时,只有当A2A1A0=111时,Y[7]才输出低电平,否
3、则为高电平,当A2A1A0=110时,Y[6]才输出低电平,否则为高电平,当A2A1A0=101时,Y[5]才输出低电平,否则为高电平,Y[4]到Y[0]同理。可见该程序设计的是3-8译码器三、共阳极数码管七段显示译码器的VHDL设计1.实体框图2.程序设计正确的程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDISPLAY_DECODERISPORT(A3,A2,A1,A0:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDENTITYDISPLAY_DECO
4、DER;ARCHITECTUREONEOFDISPLAY_DECODERISSIGNALS:STD_LOGIC_VECTOR(3DOWNTO0);BEGINS<=A3&A2&A1&A0;WITHSSELECTY<="1111110"WHEN"0000","0110000"WHEN"0001","1101101"WHEN"0010","1111001"WHEN"0011","0110011"WHEN"0100","1011011"WHEN"0101","1011111"WHEN"0110","1110000"WHEN"0111","1111111"WHE
5、N"1000","1111011"WHEN"1001","0000000"WHENOTHERS;ENDARCHITECTUREONE;3.仿真波形图4.仿真波形分析由图可知,当A3A2A1A0=0000时,输出Y[6]到Y[0]对应为1111110,即只有g不亮,数码管显示为0,A3A2A1A0=0001时,输出对应为0110000,数码管显示为1,A3A2A1A0=0010时,输出对应为1101101,数码管显示为2,其他同理,当A3A2A1A0>1001,即大于9,数码管无显示。由此可知,程序设计的是七段显示译码管。LIBRARYIEEE;USEI
6、EEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCOMPARE4IS——四位比较器PORT(IA_MORE_THAN_B:INSTD_LOGIC;——高位比较的标志位的输入IB_MORE_THAN_A:INSTD_LOGIC;IA_EQUAL_B:INSTD_LOGIC;A:INSTD_LOGIC_VECTOR(3DOWNTO0);——两个输入B:INSTD_LOGIC_VECTOR(3DOWNTO0);OA_MORE_THAN_B:OUTSTD_LOGIC;OB_MORE_THA
7、N_A:OUTSTD_LOGIC;OA_EQUAL_B:OUTSTD_LOGIC);ENDCOMPARE4;ARCHITECTUREBEHAVOFCOMPARE4ISBEGINPROCESS(IB_MORE_THAN_A,IA_EQUAL_B,IA_EQUAL_B)BEGINIF(IA_EQUAL_B='1')THEN——从最高位比较,如果高位大则停止比较输出结果,否则进行下一位比较IF(A(3)>B(3))THENOA_MORE_THAN_B<='1';OB_MORE_THAN_A<='0';OA_EQUAL_B<='0';ELSIF(A(3)
8、3))THENOA_MORE_THAN_B<='0';OB_MORE_THAN_A<='1';