译码器的vhdl设计

《译码器的vhdl设计》由会员上传分享，免费在线阅读，更多相关内容在应用文档-天天文库。

1、3-8译码器的VHDL设计1.实体框图2.程序设计正确的程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDECODER38AISPORT(A2,A1,A0,S1,S2,S3:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYDECODER38A;ARCHITECTUREONEOFDECODER38AISSIGNALS:STD_LOGIC_VECTOR(5DOWNTO0);BEGINS<=A2&A1&A0&S1&S2&S3

2、;WITHSSELECTY<="11111110"WHEN"000100","11111101"WHEN"001100","11111011"WHEN"010100","11110111"WHEN"011100","11101111"WHEN"100100","11011111"WHEN"101100","10111111"WHEN"110100","01111111"WHEN"111100","11111111"WHENOTHERS;ENDARCHITECTUREONE;3.仿真波形图4.仿真波形分析当S1S2S3=10

3、0时，只有当A2A1A0=111时，Y[7]才输出低电平，否则为高电平，当A2A1A0=110时，Y[6]才输出低电平，否则为高电平，当A2A1A0=101时，Y[5]才输出低电平，否则为高电平，Y[4]到Y[0]同理。可见该程序设计的是3-8译码器三、共阳极数码管七段显示译码器的VHDL设计1.实体框图2.程序设计正确的程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDISPLAY_DECODERISPORT(A3,A2,A1,A0:INSTD_LOGIC;Y:OUTSTD_

4、LOGIC_VECTOR(6DOWNTO0));ENDENTITYDISPLAY_DECODER;ARCHITECTUREONEOFDISPLAY_DECODERISSIGNALS:STD_LOGIC_VECTOR(3DOWNTO0);BEGINS<=A3&A2&A1&A0;WITHSSELECTY<="1111110"WHEN"0000","0110000"WHEN"0001","1101101"WHEN"0010","1111001"WHEN"0011","0110011"WHEN"0100","1011011"WHE

5、N"0101","1011111"WHEN"0110","1110000"WHEN"0111","1111111"WHEN"1000","1111011"WHEN"1001","0000000"WHENOTHERS;ENDARCHITECTUREONE;3.仿真波形图4.仿真波形分析由图可知，当A3A2A1A0=0000时，输出Y[6]到Y[0]对应为1111110，即只有g不亮，数码管显示为0，A3A2A1A0=0001时，输出对应为0110000，数码管显示为1，A3A2A1A0=0010时，输出对应为1101101，

6、数码管显示为2，其他同理，当A3A2A1A0>1001，即大于9，数码管无显示。由此可知，程序设计的是七段显示译码管。