数字电子钟逻辑电路设计_南理工

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1、目录一、设计简介·························································2二、设计任务·························································3三、数字钟实物图·····················································4四、各组成单元的电路及工作原理·······································51、振荡器··

2、·························································52、计数器···························································6(1)分、秒计数器·····················································6(2)时计数器·························································83、译

3、码显示电路·····················································94、校时电路·························································105、整点报时电路·····················································11五、数字电子钟原理图················································13六、元件表··

4、························································14七、设计心得························································15八、参考文献························································16设计简介数字钟是一种用数字电路技术实现时、分、秒计时的装置，与机械式时钟相比具有更高的准确性和直观性，且无机械装置，具有更长的使用寿命，

5、因此得到了广泛的使用数字电子钟，从原理上讲是一种典型的数字电路，其中包括了组合逻辑电路和时序电路。此次设计数字电子钟就是为了了解数字电子钟的原理，从而学会制作数字电子钟。而且通过数字电子钟的制作进一步的了解各种在制作中用到的中小规模集成电路的作用及实用方法。且由于数字钟包括组合逻辑电路和时序电路。通过它可以进一步学习与掌握各种组合逻辑电路与时序电路的原理与使用方法。数字电子钟同以下几部分组成：石英晶体振荡器、分频器、秒脉冲发生器、校正电路、60进制的秒、分计时器和24进制计时计数器以及秒、分、时的译码显

6、示部分等。设计任务一、技术要求1、该设备能直接显示“时”、“分”、“秒”，24小时为一个计时周期；2、当电路走时错误时，电路具有校时功能；3、电路具有整点报时功能，报时声响为四低一高，最后一响正好为正点。二、概述与基本组成数字钟是一个将时、分、秒显示给人的视觉器官的计时装置。它的计时周期为24小时，显示满刻度为23时59分59秒，另外还有校时和报时功能。所以，数字钟主要由脉冲源、计数器、译码器、数码管、校时电路和整点报时电路组成。如图一所示：数字钟实物图各组成单元的电路及工作原理1、振荡器振荡器是数字电

7、子钟的心脏，它是产生时间1HZ标准秒信号的电路。在此数字电子钟，用来产生1HZ标准秒信号的振荡电路是将555定时器接成多谐振荡器。该振荡器的组成如图二所示：该电路的工作原理如下：当555定时器输出(OUT)为高电平时，放电端(DIS)截止，电源端(Vcc)对电容C充电，充电回路为Vcc→R2→R1→C→地，电容两端的电压按指数规律上升，当上升到2/3Vcc时，555定时器输出变为低电平，放电端（DIS）导通。此时，电容C开始放电，随着放电的进行，电容两端的电压按指数规律下降，当电容电压下降到1/3Vcc

8、时，555定时器输出又变为高电平，放电端(DIS)截止，电容C又开始充电。如此循环下去，就会在输出端(OUT)产生幅度一定、周期一定的矩形脉冲波。根据电容充、放电时间，可以计算出图二所示用555定时器接成多谐振荡器的输出矩形脉冲波的周期计算公式为：T≈0.69(R1+2R2)C　　　　　(1)取由图二所示的元件参数，即R1=R2=10kΩ,C=47μF，计算该电路产生的矩形脉冲波的周期为：T≈0.69×(10×103+2×10×103)×4