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时间:2019-03-01
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1、SPIWISHBONEControllerJanuary2011ReferenceDesignRD1044IntroductionTheSerialPeripheralInterface(SPI)busprovidesanindustrystandardinterfacebetweenmicroprocessorsandotherdevicesasshowninFigure1.ThisreferencedesigndocumentsaSPIWISHBONEcontrollerdesignedtoprovideaninterfac
2、ebetweenamicroprocessorwithaWISHBONEbusandexternalSPIdevices.Inmastermode,theSPIcontrollercanbeconfiguredforcommunicationwithmultipleoff-chipSPIports.Inslavemode,theSPIsup-portscommunicationswithanoff-chipSPImaster.Asasimpleserialport,theSPIusesfewFPGAresources(seeTa
3、ble6)andlittleboardspaceforwires.ThisSPIreferencedesignusesonlythreepins(clock,datain,anddataout)plusoneselectforeachslavedevice.ASPIisagoodchoiceforcommunicatingwithlow-speeddevicesthatareaccessedintermittentlyandtransferdatastreamsratherthanreadingandwritingtospeci
4、ficaddresses.ASPIisanespeciallygoodchoiceifyoucantakeadvantageofitsfull-duplexnature,whichsendsandreceivesdataatthesametime.Figure1.UsingtheSPIWISHBONEControllertoConnecttoPeripheralsFPGAPeripheralSlaveSPISPIWISHBONEMicroprocessorController(MasterMode)PeripheralWISHB
5、ONESlaveSPIBothVerilogandVHDLversionsofthereferencedesignareavailable.Latticedesigntoolsareusedforsynthesis,placeandrouteandsimulation.ThedesigncanbetargetedtomultipleLatticedevicefamilies.ItssmallsizemakesitportableacrossdifferentFPGAorCPLDarchitectures.Thisdesignas
6、sumestheuserhasexperiencewithWISHBONEcontrollers.InformationavailableinthedocumentslistedintheReferencessectionisnotrepeatedinthisdocument.TheoryofOperationOverviewThisSPIWISHBONEcontrollerprovidesaninterfacebetweenamicroprocessorwithaWISHBONEbusandaSPIdevice.Thecont
7、rollercaneitheractastheSPIMasterorSPISlavedevice.TheselectionoftheMasterorSlavemodeisdoneusingparametersintheHDLcode.Thedesignusesasinglemodule.TheSPIWISHBONEreferencedesignprovidesstandard,fully-configurableSPIportsincluding:•WISHBONEB.3interface•Slaveandmastermodes
8、.Mastermodecancontroluptoeightslaves.Morecanbeaddedifdesired.•Interruptrequesttotheprocessor,configurableforavarietyofstatusconditi
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