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1、VHDLCodingStyle Targetat Performance/Delay/LCUsage2021/7/30P.1VHDLDesignFlow-VSARVHDLEntryUseanyTextEditortoinputyourdesignSynthesisUseanyVHDLCompilertoconvertyourlanguagedesigntoGatelevelwithoptimizationintermofSpeed/AreaArchitectureSynthesisTomapthelogicto
2、AlteraDeviceArchitecturee.g.LUT,Carry/CascadeChain,EAB......(furtherlogicoptimization)ResultConfiguretheAlteraDeviceanddoonboarddebugging,prototypingorproduction2021/7/30P.2cont...VHDLEntrySynthesisArchitectureSynthesisResultWhyAlteraFAEtellsmethis?Wooo.....
3、...ItisImportant?ItisnotImportant?DoIneedtoUnderstandorRememberit?!?!No.Itisuseless.Idon’tknowwhatitiseither.Ijustwanttomakefunonyou!2021/7/30P.3WhatdoyouexpectfromVHDL?WhatdoyouexpectfromVHDLCompiler?IwantSpeedIwantsmallerusageofLCDesignastatemachineinVHDLi
4、smuchmoreeasier2021/7/30P.4UsetheSuitableCodingStyleDifferentcodingstylehasdifferentperformanceOR2021/7/30P.5Issue1LatchorFlipflop2021/7/30P.6HowtodotheLatchEntitytest1isport(clk,d,reset:inbit;q:outbit);endtest1;architecturetest1_bodyoftest1isbeginprocess(cl
5、k,d,reset)beginif(reset=‘1’)thenq<=‘0’;elsif(clk=‘1’)thenq<=d;endif;endprocess;endtest1_body;ResettakeoverthecontrolfirstClktakethecontrolsecondWithintheprocessexcuteinstep-by-step2021/7/30P.7ThisisaLATCH2021/7/30P.8Entitytest1isport(clk,d,reset:inbit;q:outb
6、it);endtest1;architecturetest1_bodyoftest1isbeginprocess(clk)beginif(reset=‘1’)thenq<=‘0’;elsif(clk=‘1’)thenq<=d;endif;endprocess;endtest1_body;disnotincludedinsensitivitylistit’schangewillnotchangetheoutput2021/7/30P.9IgetaFlip-FlopnotaLATCH2021/7/30P.10Why
7、IhaveaFlip-FlopnotaLatchLatchwithaSensitivitylistprocess(clk,d,reset)Flip-FlopwithaSensitivitylistprocess(clk)Q:WhatistheSensitivitylistusefor?A:TheOUTPUTchangewhentheSensitivitylistchange2021/7/30P.11MoreDetailprocess(clk,d,reset)thissaythattheOUTPUTchangew
8、heneitherclk,dorresetchange,ifclk,dorresetnotchange,thenmaintaintheoutputwhatkindofdevicewillprovidethisfunction?LATCH2021/7/30P.12process(clk)thissaythatOUTPUTchangewhenCLKchange,ifclkdoesnotch
