四位二进制计数器vhdl程序.doc

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1、LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;entityCNT4isPORT(cp,r:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));endcNT4;ARCHITECTUREONEOFCNT4ISSIGNALcount:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(cp,r)BEGINifr='0'thencount<="0000";elsiFcp'EVENTANDcp='1'THENifcount="

2、1111"THENcount<="0000";ELSEcount<=count+1;ENDIF;endif;ENDPROCESS;q<=count;endONE;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;entityCNT4isPORT(cp,r:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));endcNT4;ARCHITECTUREONEOFCNT4ISSIGNALcount:STD_LOGIC_VECTOR(3DOWNTO0);BE

3、GINPROCESS(cp,r)BEGINifr='0'thencount<="0000";elsiFcp'EVENTANDcp='1'THENifcount="0000"THENcount<="1111";ELSEcount<=count-1;ENDIF;endif;ENDPROCESS;q<=count;endONE;