数字逻辑设计及应用教学英文课件：Lec03.ppt

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1、1DigitalLogicDesignandApplicationChenYanLecture#3CMOSElectricalBehaviorUESTC,Spring20112LastLecturePositiveLogicandNegativeLogicCMOSLogic3LastLectureNAND,NOR,AOI,OAI2ntransistorsforn-inputgateNotice:theadditive“on”resistanceoftransistorsPMOS网络NMOS网络OutI1InI1In……LastLectureTransmis

2、sionGatesTri-StategatesDrainopengatesSchmitt-triggerinput453.4ElectricalBehaviorofCMOSCircuitsDigitalanalysisworksonlyifcircuitsareoperatedinspec:PowersupplyvoltageTemperatureInput-signalqualityOutputloadingMustdosome“analog”analysistoprovethatcircuitsareoperatedinspec.Fan-inspecsFa

3、n-outspecsTiminganalysis(setupandholdtimes)63.4ElectricalBehaviorofCMOSCircuitsOverviewLogicVoltageLevelsDCNoiseMarginsFan-OutSpeedPowerConsumptionNoiseElectrostaticDischarge(静电放电)Open-DrainOutputsThreeStateOutputsnotlogical73.4ElectronicBehaviorofCMOSCircuitsANANDGateDataSheetsandS

4、pecifications(P99Table3-3)83.5CMOSSteady-StateElectricalBehavior3.5.1LogicLevelsandNoiseMarginsVDD=+5.0VVOUTVINTpTn01019103.5CMOSSteady-StateElectricalBehavior3.5.1LogicLevelsSpecificationsHIGHABNOMALLOWVOLmaxVOHminTheinputvoltagesaredeterminedmainlybyswitchingthresholdsofthetransis

5、tors,whiletheoutputvoltagesaredeterminedmainlybythe“on”resistanceofthetransistors.VILmaxVIHminVCC−0.1VGND+0.1V70%VCC30%VCCPower-supplyrails:VCCandGND113.5.1DCNoiseMargin30%VCC−0.1VHIGHABNOMALLOWVOLmaxVILmaxVIHminVOHminHigh-stateDCnoisemarginLow-stateDCnoisemargin3.5CMOSSteady-StateE

6、lectricalBehavior3.5.2CircuitBehaviorwithResistiveLoadsResistiveLoadsdiscreteresistorTTLandothernon-CMOSloadCurrentconsumptiondevice12whichrequirenontrivialamountsofcurrenttooperateCMOSdevicehasveryhighinputimpedance,itbehavesasideallogicdevice.3.5.2CircuitBehaviorwithResistiveLoads

7、13WhentheoutputofCMOScircuitisconnectedtoaresistiveload,theoutputbehaviorisnotasidealaswedescribedpreviously.Theonresistor(non-zero)willleadtoanon-zerovoltagedropwhichwillcausetheL-outputvoltagegreaterthanVOLMaxortheH-outputvoltagelowerthanVOHMin.UseresistivemodeltoanalysistheCMOSci

8、rcuitbehaviorwithre