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ID:57599845
大小:1.52 MB
页数:31页
时间:2020-08-28
《数字逻辑设计及应用教学英文课件:Lec17-Chap 7.ppt》由会员上传分享,免费在线阅读,更多相关内容在教育资源-天天文库。
1、1DigitalLogicDesignandApplicatonLecture#17LatchesandFlip-FlopsUESTC,Spring20132再谈串行输入加法器的实现QDQCXYCISiCi+1XiYiCiSCOCLK暂存XYCICOSCi+1SiXiYiCi时钟控制电平有效还是边沿有效?串行输入、串行输出注意:时钟同步IterativeVs.Sequential3IterativeVersusSequentialCircuitsC0C4X0Y0X1Y1X2Y2X3Y3S0S1S2S347.2Lat
2、chesandFlip-FlopsLatcheschangeitsoutputsatanytime(enableinputisasserted).Flip-FlopschangeitsoutputsonlywhentheclockchangesCLKPositive-EdgeRising-EdgeNegative-dgeFalling-EdgeLeveltriggeredEdge-triggered,ET57.2.5Edge-TriggeredDFlip-FlopsDQCQDQCQQQLDCLKmasterslaveQ
3、mWhenCLK=0,WhenCLK=1,QmfollowsD;Qisunchanging.Qmisunchanging,Q=QmuntilthenextrisingCLKedge1.Master/Slave,Positive-edge-triggeredQchangesonlywhenCLKrisesfrom0to16TimingDiagramformaster-slaveDF/FDCLKQQmDQCQDQCQQQLDCLKQmQ=D()7DCLKQDQCLKQLogicSymbolEdge-Triggered8DC
4、LKQDCLKQDLatchDFlip-Flop——edge-triggeredwhenCLKisasserted对信号扰动不敏感受信号扰动影响9Dflip-floptimingparametersPropagationdelay(fromCLK)tpLH(CQ)tpHL(CQ)tsetup建立时间thold保持时间Setuptime(DbeforeCLK)Holdtime(DafterCLK)DCLKQ在时钟上升边沿附近有一个时间窗口,在此窗口时间内,数据输入D不能改变,否则电路进入亚稳态。从输入信号D到来时刻至信号
5、D达到稳定所持续的时间。从输入信号D达到稳定至信号D被锁存器接受所持续的时间。102.Negative-Edge-TriggedDFlip-FlopDQCQDQCQQQNDCLKDQCLKQDQCQDQCQQQLDCLKPositive-edge-triggered3.DFlip-Flopwithpresetandclear同步(synchronous)是指与时钟同步,即时钟触发条件满足时检测清零(置位)信号是否有效,有效则在下一个时间周期的触发条件下,执行清零(置位);异步(asynchronous)是清零(置位)信
6、号有效时,无视触发脉冲,立即清零(置位)。11123.DFlip-FlopwithpresetandclearCLKQQLDPR_LCLR_LPRDQCLKQCLRasynchronousinputsbehaviorlikethesetandresetinputsonS-Rlatch.100111110110013TimingDiagramforDflip-flopwithpresetandclearCLKPR_LCLR_LQL3.DFlip-Flopwithpresetandclearsynchronousinput
7、s:PR(preset)andCLR(cleardependontheCLK14DQCLKQDinResetCLK?R有效,Q=0R无效,Q=DinDinReset_L?154.CommercialTTLDFlip-Flops(74LS74)P535Figure7-20PR_LCLR_LCLKDQQN维持阻塞结构Smallerandfaster165.CMOSedge-triggeredDcircuitUsestransmissiongatesinfeedbackloopsQDCLKDCLKTwofeedbackloo
8、ps(masterandslavelatches)MasterSlave177.2.6DFlip-FlopwithEnable2-inputMultiplexerDQCLKQDENCLKQQLIfENisasserted,theexternalDinputisselected;ifENisnegated,thecurrentout
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