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1、LIBRARYIEEE;--IncludeLibrariesforstandardlogicdatatypesUSEIEEE.STD_LOGIC_1164.ALL;--EntitynamenormallythesameasfilenameENTITYgate_networkIS--Ports:DeclaresmoduleinputsandoutputsPORT(A,B,C:INSTD_LOGIC;--StandardLogicVector(Arrayof4Bits)D:INSTD_LOGIC_VECTOR(3DOWNTO0);--Out
2、putSignalsX,Y:OUTSTD_LOGIC);ENDgate_network;--DefinesinternalmodulearchitectureARCHITECTUREbehaviorOFgate_networkISBEGIN--Concurrentassignmentstatementsoperateinparallel--D(1)selectsbit1ofstandardlogicvectorDX<=AANDNOT(BORC)AND(D(1)XORD(2));--Processmustdeclareasensitivi
3、tylist,--Inthiscaseitis(A,B,C,D)--ListincludesallsignalsthatcanchangetheoutputsPROCESS(A,B,C,D)BEGIN--StatementsinsideprocessexecutesequentiallyY<=AANDNOT(BORC)AND(D(1)XORD(2));ENDPROCESS;ENDbehavior;Figure6.1StateDiagramforst_machexampleLIBRARYIEEE;USEIEEE.STD_LOGIC_116
4、4.ALL;LIBRARYAltera_mf;USEaltera_mf.altera_mf_components.all;ENTITYamemoryISPORT(read_data:OUTSTD_LOGIC_VECTOR(7DOWNTO0);memory_address:INSTD_LOGIC_VECTOR(2DOWNTO0);write_data:INSTD_LOGIC_VECTOR(7DOWNTO0);Memwrite:INSTD_LOGIC;clock,reset:INSTD_LOGIC);ENDamemory;ARCHITECT
5、UREbehaviorOFamemoryISBEGINdata_memory:altsyncram--AltsyncrammemoryfunctionGENERICMAP(operation_mode=>“SINGLE_PORT”,width_a=>8,widthad_a=>3,lpm_type=>“altsyncram”,outdata_reg_a=>"UNREGISTERED",--Readsinmiffileforinitialdatavalues(optional)init_file=>"memory.mif",intended
6、_device_family=>“Cyclone”)PORTMAP(wren_a=>Memwrite,clock0=>clock,address_a=>memory_address(2DOWNTO0),data_a=>write_data,q_a=>read_data);ENDbehavior;Figure6.2SchematicofHierarchicalDesignENTITYhierarchISPORT(clock_25Mhz,pb1:INSTD_LOGIC; pb1_single_pulse:OUTSTD_LOGIC);ENDh
7、ierarch;ARCHITECTUREstructuralOFhierarchIS--DeclareinternalsignalsneededtoconnectsubmodulesSIGNALclock_1MHz,clock_100Hz,pb1_debounced:STD_LOGIC;COMPONENTdebounce--UseComponentstoDefineSubmodulesandParametersPORT(pb,clock_100Hz:INSTD_LOGIC; pb_debounced:OUTSTD_LOGIC);ENDC
8、OMPONENT;COMPONENTonepulsePORT(pb_debounced,clock:INSTD_LOGIC; pb_single_pulse:OUTSTD_LOGIC);ENDCOMPONE
