数字电路4选1选择器、3位比较器VHDL代码.doc

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1、4选1选择器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYsjxzISPORT(G,A1,A0:INSTD_LOGIC;D0,D1,D2,D3:INSTD_LOGIC;Y,YB:OUTSTD_LOGIC);ENDsjxz;ARCHITECTUREbehavOFsjxzISSIGNALcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb<=A1&A0;PROCESS(G,comb,D0,D1,D2,D3)BEGINIFG='0'THENCASEcombISWHEN"00"=>

2、Y<=D0;YB<=NOTD0;WHEN"01"=>Y<=D1;YB<=NOTD1;WHEN"10"=>Y<=D2;YB<=NOTD2;WHEN"11"=>Y<=D3;YB<=NOTD3;WHENOTHERS=>Y<='0';YB<='1';ENDCASE;ELSEY<='0';YB<='1';ENDIF;ENDPROCESS;ENDbehav;3位比较器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcomp3ISPORT(A:INSTD_LOGIC_VECTOR(2DOWNTO0);B:INSTD_L

3、OGIC_VECTOR(2DOWNTO0);YA,YB,YC:OUTSTD_LOGIC);ENDcomp3;ArCHITECTUREbehaveOFcomp3ISBEGINPROCESS(A,B)BEGINIF(A>B)THENYA<='1';YB<='0';YC<='0';ELSIF(A

4、TYjuzhongISPORT(A,B0,B1:INSTD_LOGIC;G,R:OUTSTD_LOGIC);ENDjuzhong;ARCHITECTUREaofjuzhongISBEGING<=AAND(B0ORB1);R<=AOR(B0ANDB1);ENDa;