16选1选择器的层次化vhdl设计

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1、实验名称：实验10层次化设计——VHDL一、16选1选择器的层次化VHDL设计1、实体框图2、程序设计（1）4选1选择器子程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMUX41AISPORT(D3,D2,D1,D0,A1,A0,EN:INSTD_LOGIC;Y:OUTSTD_LOGIC);ENDENTITYMUX41A;ARCHITECTUREONEOFMUX41AISBEGINY<=D0WHENA1='0'ANDA0='0'ANDEN='0'ELSED1WHENA1='0

2、'ANDA0='1'ANDEN='0'ELSED2WHENA1='1'ANDA0='0'ANDEN='0'ELSED3WHENA1='1'ANDA0='1'ANDEN='0'ELSE'Z';ENDARCHITECTUREONE;（2）2—4译码器子程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDE24AISPORT(A1,A0:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDENTITYDE24A;ARCHITECTUREONE

3、OFDE24AISSIGNALS:STD_LOGIC_VECTOR(1DOWNTO0);BEGINS<=A1&A0;WITHSSELECTY<="1110"WHEN"00","1101"WHEN"01","1011"WHEN"10","0111"WHEN"11";ENDARCHITECTUREONE;（3）4输入或门子程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYOR41AISPORT(A,B,C,D:INSTD_LOGIC;Y:OUTSTD_LOGIC);ENDENTITY

4、OR41A;ARCHITECTUREONEOFOR41AISBEGINY<=AORBORCORD;ENDARCHITECTUREONE;（4）顶层文件LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMUX161AISPORT(DIN:INSTD_LOGIC_VECTOR(0TO15);SIN:INSTD_LOGIC_VECTOR(3DOWNTO0);YOUT:OUTSTD_LOGIC);ENDENTITYMUX161A;ARCHITECTURETOPOFMUX161AISCOMPO

5、NENTMUX41APORT(D3,D2,D1,D0,A1,A0,EN:INSTD_LOGIC;Y:OUTSTD_LOGIC);ENDCOMPONENTMUX41A;COMPONENTDE24APORT(A1,A0:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCOMPONENTDE24A;COMPONENTOR41APORT(A,B,C,D:INSTD_LOGIC;Y:OUTSTD_LOGIC);ENDCOMPONENTOR41A;SIGNALEN3,EN2,EN1,EN

6、0,Q3,Q2,Q1,Q0:STD_LOGIC;BEGINU1:MUX41APORTMAP(D0=>DIN(0),D1=>DIN(1),D2=>DIN(2),D3=>DIN(3),A1=>SIN(1),A0=>SIN(0),EN=>EN0,Y=>Q0);U2:MUX41APORTMAP(D0=>DIN(4),D1=>DIN(5),D2=>DIN(6),D3=>DIN(7),A1=>SIN(1),A0=>SIN(0),EN=>EN1,Y=>Q1);U3:MUX41APORTMAP(D0=>DIN(8),D1=>DIN(9),

7、D2=>DIN(10),D3=>DIN(11),A1=>SIN(1),A0=>SIN(0),EN=>EN2,Y=>Q2);U4:MUX41APORTMAP(D0=>DIN(12),D1=>DIN(13),D2=>DIN(14),D3=>DIN(15),A1=>SIN(1),A0=>SIN(0),EN=>EN3,Y=>Q3);U5:DE24APORTMAP(A1=>SIN(3),A0=>SIN(2),Y(0)=>EN0,Y(1)=>EN1,Y(2)=>EN2,Y(3)=>EN3);U6:OR41APORTMAP(A=>Q0,

8、B=>Q1,C=>Q2,D=>Q3,Y=>YOUT);ENDARCHITECTURE;3、仿真波形图4、仿真波形分析由图可知，当控制信号SIN=0时，输出DIN0，当SIN=1，输出DIN1，当SIN=2，输出DIN2，……当SIN=15输出DIN15，由此可见，此程序是一个16选一选择器。