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1、......LaboratoryExercise1Switches,Lights,andMultiplexersED实验参与答案Part1libraryieee;useieee.std_logic_1164.all;entitypart1isport(SW:instd_logic_vector(17downto0);LEDR:outstd_logic_vector(17downto0));endpart1;architectureBehaviorofpart1isbeginLEDR<=SW;endBehavior;参考材料...
2、...part2libraryieee;useieee.std_logic_1164.all;--a2to1multiplexerentityentitymux21isport(in_x,in_y,in_s:instd_logic;out_m:outstd_logic);endmux21;--a2to1multiplexerarchitecturearchitecturestructuralofmux21issignalu,v:std_logic;beginu<=in_xand(notin_s);v<=in_yandin_s;o
3、ut_m<=uorv;endstructural;--aeight-bitwide2to1multiplexerlibraryieee;useieee.std_logic_1164.all;参考材料......--eight-bitwide2to1multiplexerentityentitymux21_8bitisport(SW:instd_logic_vector(17downto0);--SW:instd_logic_vector(15downto8);--SW:instd_logic_vector(17downto17)
4、;LEDR:outstd_logic_vector(7downto0));endmux21_8bit;--eight-bitwide2to1multiplexerarchitecturearchitectureStructuralofmux21_8bitiscomponentmux21port(in_x,in_y,in_s:instd_logic;out_m:outstd_logic);endcomponent;beginU1:mux21portmap(in_x=>SW(0),in_y=>SW(8),in_s=>SW(17),o
5、ut_m=>LEDR(0));U2:mux21portmap(in_x=>SW(1),in_y=>SW(9),in_s=>SW(17),out_m=>LEDR(1));U3:mux21portmap(in_x=>SW(2),in_y=>SW(10),in_s=>SW(17),out_m=>LEDR(2));U4:mux21portmap(in_x=>SW(3),in_y=>SW(11),in_s=>SW(17),参考材料......out_m=>LEDR(3));U5:mux21portmap(in_x=>SW(4),in_y=
6、>SW(12),in_s=>SW(17),out_m=>LEDR(4));U6:mux21portmap(in_x=>SW(5),in_y=>SW(13),in_s=>SW(17),out_m=>LEDR(5));U7:mux21portmap(in_x=>SW(6),in_y=>SW(14),in_s=>SW(17),out_m=>LEDR(6));U8:mux21portmap(in_x=>SW(7),in_y=>SW(15),in_s=>SW(17),out_m=>LEDR(7));endStructural;part3l
7、ibraryieee;useieee.std_logic_1164.all;--a2to1multiplexerentityentitymux21isport(in_x,in_y,in_s:instd_logic;out_m:outstd_logic);endmux21;--a2to1multiplexerarchitecturearchitecturestructuralofmux21is参考材料......signalsignal_u,signal_v:std_logic;beginsignal_u<=in_xand(not
8、in_s);signal_v<=in_yandin_s;out_m<=signal_uorsignal_v;endstructural;libraryieee;useieee.std_logic_1164.all;--a5to1multiplexerentity
