返回
An FPGA-based Accelerator Implementation for Deep Convolutional Neural Networks

An FPGA-based Accelerator Implementation for Deep Convolutional Neural Networks

ID：40707362

大小：2.82 MB

页数：4页

时间：2019-08-06

An FPGA-based Accelerator Implementation for Deep Convolutional Neural Networks_第1页
An FPGA-based Accelerator Implementation for Deep Convolutional Neural Networks_第2页
An FPGA-based Accelerator Implementation for Deep Convolutional Neural Networks_第3页
An FPGA-based Accelerator Implementation for Deep Convolutional Neural Networks_第4页
资源描述：

《An FPGA-based Accelerator Implementation for Deep Convolutional Neural Networks》由会员上传分享，免费在线阅读，更多相关内容在学术论文-天天文库。

1、20154thInternationalConferenceonComputerScienceandNetworkTechnology(ICCSNT2015)AnFPGA-basedAcceleratorImplementationforDeepConvolutionalNeuralNetworks12YongmeiZhouJingfeiJiangCollegeofComputerCollegeofComputerNationalUniversityofDefenseTechnologyNationalUniversityofDefenseTechnologyChangsha,ChinaCh

2、angsha,Chinayongmei0102@163.comjingfeijiang@126.comAbstract—Deepconvolutionalneuralnetworks(CNN)istimeofprocessingoneinputfeaturemap,ourworkis16.42highlyefficientinimagerecognitiontaskssuchasMNISTdigittimesfasterthantheMATLAB/CPUcode.recognition.AcceleratorsbasedonFPGAplatformareproposedsincegenera

3、lpurposeprocessorisdisappointingintermsofII.BACKGROUNDperformancewhendealingwithrecognitiontasks.Recently,anoptimizedFPGA-basedacceleratordesign(work1)hasbeenA.CNNBasicsproposedclaimingbestperformancecomparedwithexistingimplementations.Butastheauthoracknowledged,performanceGivenapreprocessednatural

4、image(alsocalledaninputcouldbebetteriffixedpointpresentationandcomputationfeaturemap),aconvolutionalvalueisthedotproductofaelementshadbeenused.Inspiredbyitsmethodologyinpixel-matrice(partoftheinputfeaturemap)andaweight-implementingtheAlexnetconvolutionalneuralnetwork,wematrice.Figure1showsanexample

5、ofaconvolutionallayerimplementa5-layeracceleratorforMNISTdigitrecognitionwithoneinput-feature-map,threeweight-matrix(ofasizeoftaskusingthesameVivadoHLStoolbutusing11-bitsfixed2*2)andthreeoutput-feature-maps;Code1showshowthepointprecisiononaVirtex7FPGA.Wecompareperformanceconvolutionaloperationcanbe

6、expressedinCcodeinHLSonFPGAplatformwiththeperformanceofthetargetCNNontool.MATLAB/CPUplatform;wereachaspeedupof16.42.Ourimplementationrunsat150MHzandreachesapeakperformanceof16.58GMACS.SinceourtargetCNNissimpler,weusemuchlessresourcethanwork1hasused.Keywords—FPGA;ConvolutionalNeuralNetwork;fixed-poi

7、ntarithmetic;HLSI.INTRODUCTIONDeepconvolutionalneuralnetworks(CNN)iswildlyusedinimagerecognitiontaskssuchasMNISTdigitrecognition[1].Generalpurposeprocessorisnotreallyefficientindealingwithsuchrecognitiontas

当前文档最多预览五页，下载文档查看全文

此文档下载收益归作者所有

当前文档最多预览五页，下载文档查看全文
温馨提示：
1. 部分包含数学公式或PPT动画的文件，查看预览时可能会显示错乱或异常，文件下载后无此问题，请放心下载。
2. 本文档由用户上传，版权归属用户，天天文库负责整理代发布。如果您对本文档版权有争议请及时联系客服。
3. 下载前请仔细阅读文档内容，确认文档内容符合您的需求后进行下载，若出现内容与标题不符可向本站投诉处理。
4. 下载文档时可能由于网络波动等原因无法下载或下载错误，付费完成后未能成功下载的用户请联系客服处理。