2_PPT_Architecting Phase Change Memory As DRAM Alternative

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1、ArchitectingPhaseChangeMemoryasaScalableDRAMAlternativeKeyvanNayyeriBasedonthepaperpublishedinISCA2009,Austin,Texas(ISBN:978-1-60558-526)VolatileMemoryNon-VolatileChargeMemoryMemoryResistiveMemoryLimitationswithchargememoryUseresistivememoryPhaseChangeMemory(PCM)IBM’sPCMBitlineMetalHeaterPhaseChan

2、geMaterialMetalAccessDeviceCurrentResetSetTimePCMisproposedasagoodFlashreplacement.PCMasMainMemoryBufferOrganizationRestructuringPCMPartialWritesPCMDeploymentCPUCPUCPUMemoryMemoryMemoryControllerControllerControllerDRAMDRAMDRAMPCMPCMPCMDRAMDRAMDRAMPCMPCMPCMExperimentalMethodologySESCSimulatorCore0

3、Core1Core2Core332KB132KB132KB132KB132KB432KB432KB432KB4-wayinstruction-wayinstruction-wayinstruction-wayinstruction-waydata-waydata-waydata-waydata4MB8-way400MHzSDRAMParallelWorkloadsfftSPLASH-2radixoceanartSPECOpenMPequakeswimcgNASismgDelayandTimingFactorsEnergyDensityEnduranceTechnologyParameter

4、sLatencyEnergyBaselineDRAM-StyleBufferingPCMPerformance(2048B×1Buffer)3.532.52Delay1.5Energy1NormalizedtoDRAM0.50cgismgfftradoceartequswiavgPCMEnergy(2048B×1Buffer)0.50.40.30.2NormalizedtoDRAM0.10cgismgfftradoceartequswiavgBufferOrganization•On-ChipBuffers•NarrowRows•MultipleRowsDataArraysDataArra

5、ysSenseSenseAmplifiers(Buffer)AmplifierI/OLatches(Buffer)I/OPCMPerformance(512B×4Buffer)1.81.61.41.21Delay0.8Energy0.6NormalizedtoDRAM0.40.20cgismgfftradoceartequswiavgPCMEnergy(512B×4Buffer)0.80.70.60.50.40.3NormalizedtoDRAM0.20.10cgismgfftradoceartequswiavgPartialWritesWearMechanismsPCMEndurance

6、(512B×4Buffer)161412108DiffLineYearsDiffWord6420cgismgfftradoceartequswiavgPCMEndurance(512B×4Buffer)10.80.6DirtyLines0.4DirtyWords0.2FractionofBufferWidth(512B)0cgismgfftradoceartequswiavgAdvantagesNon-VolatileMainMemoryInstantaneousBootorHibernationInexpensiveCheckpointing