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A 2-terminal vertical memory cell for large-volume random access memory applications—revised-0225

A 2-terminal vertical memory cell for large-volume random access memory applications—revised-0225

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时间：2019-07-29

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1、A2-terminalverticalmemorycellforlargevolumerandomaccessmemoryapplicationsXiaodongTong,JunLuo,HaoWu,LichuanZhao,GuileiWang,HuicaiZhongandQingqingLiangInstituteofMicroelectronicsofChineseAcademyofSciencesBeijing,Chinatongxiaodong@ime.ac.cn2Abstract—Randomaccessmemorycellwith1F(Fisthelen

2、gthofhalfpitch)activecellareatoincreasetheintegrationdensityandII.NEWMEMORYCELLCONCEPTsimplifytheprocessflowisproposedinthiswork.Deca-nanosecondlevelprogrammingcharacterizationformemorycellsAsshowninFigure1(a),thenewmemorycellusesasimplepreparedbysimpleCMOS-compatibleprocesswasconduct

3、ed.verticalPNPNdiodestructure.ItexhibitsahysteresisloopasHighcyclicenduranceandgoodanti-disturbcapabilityoftheshowninFigure1(b),whichiswellknownaslatch-upeffectinproposedmemorycellwasdemonstrated.Moreover,thememoryCMOStechnology[3].Whenthevoltagebetweenanodeandarraywithcross-pointdesi

4、gnintegratedwiththeproposedcellscathode(VAC)increasesintheforwarddirection,thememorywasstudiedandsimulated,whichverifiesthatthememorycellcellstaysatalow-conductancebranchuntilVACincreasestohasgreatpotentialfortheapplicationsoflargevolume,lowcostthelatch-upvoltage(VLU).AtVLU,theinheren

5、tpositiveembeddedorstandalonememory.feedbackhappensandthecurrentflowingthroughthememorycell(IA)increasessignificantly.Then,thememorycellgetsintoI.INTRODUCTIONahigh-conductancebranchandislatcheduntilVACreturnstoARGEvolumerandomaccessmemoryisanindispensablethelatch-downvoltage(VLD)asVAC

6、decreasesinreverseLpartinhighperformanceelectronicsystem.Dynamicdirection,resultinginabi-stableregionbetweenVLDandVLUrandomaccessmemory(DRAM)with1T1Cunitisthe[4].Thememorizationmechanismisasfollowing.WhenVACmainstreaminthelargevolumerandomaccessmemoryregionisappliedatastandbyvoltage(V

7、ST)betweenVLDandVLU,[1].TheperformanceoftheconventionalDRAMisprimarilytherearetwostablestatesfortheleakagecurrentthatcanbelimitedbythepassivecapacitorwhichactsasthestoragedefinedas“1”or“0”(I1orI0respectively).“1”or“0”statecandevicewithoutaninternalgain.DRAMreadingoperationisbestablyco

8、nserv

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