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1、`defineSRAM_SIZE8`timescale1ns/1ns//FORSRAMINTERFACECONTROLmoduleSRAM_INTERFACE(in_data,//INPUTDATA out_data,//OUTPUTDATA fiford,//FIFOREADCONTROLLOWVOLTAGE fifowr,//FIFOWRITECONTROLLOWVOLTAGE nfull, nempty, address,//SENTSRAMADDRESSBU
2、S sram_data,//SRAMDATABUS rd,//SRAMREADSINGALENABLELOWVOLTAGE wr,//SRAMWRITEENABLELOWVOLTAGE clk,//systemclk rst);//globalresetsingal,lowvoltageinput fiford,fifowr,clk,rst;input[7:0]in_data;output[7:0]out_data;reg[7:0] in_data_buf,out_data_buf;/
3、/inputandoutputbufferoutput reg nfull,nempty;outputrd,wr;inout[7:0]sram_data;outputreg[10:0]address;reg[10:0]fifo_wp,fifo_rp;reg[10:0]fifo_wp_next,fifo_rp_next;regnear_full,near_empty;reg[3:0]state;parameteridle=4'b0000, read_ready='b0100, read='b0101, read_over='b0111,
4、 write_ready='b1000, write='b1001, write_over='b1011;always@(posedge clkornegedgerst)begin if(!rst) state<=idle; elsecase(state) idle:begin if(fifowr==0&&nfull) state<=write_ready; elseif(
5、fiford==0&&nempty) state<=read_ready; else state<=idle; end read_ready: state<=read; read:begin if(fiford==1) state<=read_over;
6、 else state<=read; end read_over: state<=idle; write_ready: state<=write; write:begin if(fifowr==1) state<=write_over;
7、 else state<=write; end write_over: state<=idle; default:state<=idle; endcaseendassignrd=~state[2];assignwr=(stat
