资源描述:
《基于fpga实现的1553b编解码verilog源代码》由会员上传分享,免费在线阅读,更多相关内容在学术论文-天天文库。
1、编码程序moduleencoder_1553(//ClockandResetenc_clk,rst_n,//Inputstx_dword,tx_csw,tx_dw,//Outputstx一busy,tx_data,tx_dval);inputi叩utenc_clk;//2Mhzencoderclock.rst_n;//Asynchronousreset.input[0:15]inputinputtx_dword;//Inputdatawordtransmit.tx_csw;//”tx_dword•’hascommandorstatusword.txdw;//’’txdword”has
2、dataword.outputtx_busy;//Encoderisnotreadytoacceptnextword.outputoutputtx_data;//Serialtransmitdataoutput.tx_dval;//Indicatesdataon”tx_data”isvalid.regcnt_en;regreg[5:0]reg[0:16Jreg15:0]cnt_cn_rcg;busy_cnt;data_reg;sync_bits;regtx_data;regtx_dval;wireparity;wire[0:40]wireenc_data;dataout://Coun
3、tnumberofclocksrequiredtoencodeandserialize//theinputdata.always@(poscdgccnc_clkorncgcdgcr$t_n)beginif(!rst_n)cnt_en<=1fb0;elseif(tx_csw
4、
5、tx_dw)ent—en<=l’bl;elseif(busy_cnt=='d38)cnt_en<=1’bO;elsecnt_en<=cnt_en;endalways@(poscdgccnc_clkorncgcdgcr$t_n)beginif(!rst_n)cnt_en_reg<=1fb0;elsecnt_en_r
6、eg<=cnt_en;endalways@(posedgeenc_clkornegedgerst_n)beginif(!rst_n)busy_cnt<=’d();elseif(cnt_cn)busy_cnt<=busy_cnt+1;elsebusy_cnt<=rd0;end//Generatebusysignalfortheuserinterface,assigntx_busy=cnt_en;//Generateparityforthegiven16bitworddata,assignparity=A(tx_dword);//Registerinputdatawordalongwit
7、hgeneratedparity,always@(posedgeenc_clkornegedgerst_n)beginif(!rst_n)data_reg<=17’h0000;elseif((tx_csw
8、
9、tx_dw)&&!cnt_en)data_reg<={tx_dword,parity};elseif(!cnt_en)data.reg<=17’h()()(X);elsedata_reg<=data_reg;end//Determinethesyncpatternbasedonwordtype,always@(posedgeenc_clkornegedgerst_n)begini
10、f(!rst_n)sync_bits<=6*b000_000;elseif(tx_csw)sync_bits<=6'blll_000;elseif(tx_dw)sync_bits<=6’b000_l11;elsesync_bits<=sync_bits;end//GenerateManchesterencodeddataforcombinedsyncpattern,//datawordandparity,assignenc_data={sync_bits,data_rcg[0],~data_rcg[0],data_reg[l],〜data_reg[l],data_regL2J,-da
11、ta_reg[2J,data_reg[3],-data_reg[3],data_regf4],-data_reg[4],data_rcg[5],〜data_reg[5],data_reg[6],〜data_reg[6],data_regl/7j,〜data_reg
12、7J,data_reg[8],〜data_reg[8J,data_regf9],-data_reg[9],data一reg[10],〜data_reg[10],data_reg[11],〜dat