systemverilog 数字系统设计.pdf

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1、DigitalSystemDesignwithSystemVerilogMarkZwoli´nskiOctober9,2009DRAFT2DRAFTContentsPreface191Introduction251.1Moderndigitaldesign........................251.2Designingwithhardwaredescriptionlanguages..........251.2.1Designautomation....................

2、.251.2.2WhatisSystemVerilog?..................261.2.3WhatisVHDL?......................261.2.4Simulation.........................271.2.5Synthesis..........................271.2.6Reusability.........................281.2.7Verification....................

3、.....281.2.8Designflow.........................291.3CMOStechnology.........................321.3.1Logicgates.........................321.3.2ASICsandFPGAs.....................331.4Programmablelogic.........................381.5Electricalproperties......

4、...................421.5.1Noisemargins.......................421.5.2Fan-out...........................44Summary.................................45Furtherreading..............................46Exercises.................................462Combinationall

5、ogicdesign472.1Booleanalgebra...........................472.1.1Values............................472.1.2Operators..........................472.1.3Truthtables.........................482.1.4RulesofBooleanalgebra..................492.1.5DeMorgan'slaw...

6、...................502.1.6Shannon'sexpansiontheorem...............502.2Logicgates.............................50DRAFT34CONTENTS2.3Combinationallogicdesign.....................522.3.1Logicminimization.....................532.3.2Karnaughmaps............

7、...........542.4Timing................................592.5Numbercodes............................602.5.1Integers...........................632.5.2Fixedpointnumbers....................632.5.3Floatingpointnumbers...................642.5.4Alphanumericch

8、aracters..................642.5.5Graycodes.........................642.5.6Paritybits..........................65Summary.................................66Furtherreading..............................66Exercises.................................6