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时间:2019-03-10
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1、iiSystemVerilogAssertionsHandbookSystemVerilogAssertionsHandbook…forFormalandDynamicVerificationPublishedby:VhdlCohenPublishingP.O.2362PalosVerdesPeninsulaCA90274-2362vhdlcohen@aol.comhttp://www.vhdlcohen.comLibraryofCongressCataloging-in-PublicationDataAC.I.P.Catalogrecordforthisbookisavailab
2、lefromtheLibraryofCongressSystemVerilogAssertionsHandbook…forFormalandDynamicVerificationISBN0-9705394-7-9Copyright©2005byVhdlCohenPublishingAllrightsreserved.Nopartofthispublicationmaybereproducedortransmittedinanyformorbyanymeans,electronicormechanical,includingphotocopying,recording,orbyany
3、informationstorageandretrievalsystem,withoutthepriorwrittenpermissionfromtheauthor,exceptfortheinclusionofbriefquotationsinareview.Printedonacid-freepaperPrintedintheUnitedStatesofAmericaPrefaceiiiContentsForeword…………………………………………………………………………………..xiSurrendraA.Dudani……………………………………………………………………xiS
4、tuartSutherland……………………………………………………………………….xiiiHarryD.Foster………………………………………………………………………..xvTarakParikh………………………………………………………………………….xviiKeithRieken……………………………………………………………………………xixYu-ChinHsu……………………………………………………………………………xxiAlainRaynaud………………………………………………………………………….xxiiiPreface………………………………………………………
5、……………………………..xxvAcknowledgements……………………………………………………………………xxixAbouttheauthors………………………………………………………………………xxxiiiDisclaimer………………………………………………………………………………….xxxv1ROLEOFSYSTEMVERILOGASSERTIONSINAVERIFICATIONMETHODOLOGY...........................................11.1HistoryofDesignVerificationmethodol
6、ogies.............................................................……21.2SystemVerilogAssertionsinverificationStrategy...................................................……...51.2.1AreAssertionsIndependentfromSystemVerilogStructures?………………………51.2.2AreAssertionsUsefulfortheDefinitionandVerificati
7、onofDesigns?..................…..61.2.2.1CapturesDesignerIntent................................................................................................71.2.2.2AllowsProtocolstobeDefinedandVerified................................
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