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1、ThePowerofAssertionsinSystemVerilogEduardCernySurrendraDudaniJohnHavlicekDmitryKorchemnyThePowerofAssertionsinSystemVerilogABCDr.EduardCernyJohnHavlicekedcerny@synopsys.comjohn.havlicek@freescale.comDr.SurrendraDudaniDr.DmitryKorchemnydudani@synopsys.comdmitry.korchemny@intel.comISBN978-1
2、-4419-6599-8e-ISBN978-1-4419-6600-1DOI10.1007/978-1-4419-6600-1SpringerNewYorkDordrechtHeidelbergLondonLibraryofCongressControlNumber:2010934904cSpringerScience+BusinessMedia,LLC2010Allrightsreserved.Thisworkmaynotbetranslatedorcopiedinwholeorinpartwithoutthewrittenpermissionofthepublisher
3、(SpringerScience+BusinessMedia,LLC,233SpringStreet,NewYork,NY10013,USA),exceptforbriefexcerptsinconnectionwithreviewsorscholarlyanalysis.Useinconnectionwithanyformofinformationstorageandretrieval,electronicadaptation,computersoftware,orbysimilarordissimilarmethodologynowknownorhereafterdeve
4、lopedisforbidden.Theuseinthispublicationoftradenames,trademarks,servicemarks,andsimilarterms,eveniftheyarenotidentifiedassuch,isnottobetakenasanexpressionofopinionastowhetherornottheyaresubjecttoproprietaryrights.Printedonacid-freepaperSpringerispartofSpringerScience+BusinessMedia(www.spring
5、er.com)PrefaceThisbookistheresultofthedeepinvolvementoftheauthorsinthedevelopmentofEDAtools,SystemVerilogAssertionstandardization,andmanyyearsofpracticalexperience.Oneofthegoalsofthisbookistoexposetheoralknowhowcirculatedamongdesignandverificationengineerswhichhasneverbeenwrittendowninitsful
6、lextent.Thebookthuscontainsmanypracticalexamplesandexercisesillustrat-ingthevariousconceptsandsemanticsoftheassertionlanguage.Muchattentionisgiventodiscussingefficiencyofassertionformsinsimulationandformalverifica-tion.Wedidourbesttovalidatealltheexamples,buttherearehundredsofthemandnotallfea
7、turescouldbevalidatedsincetheyhavenotyetbeenimplementedinEDAtools.Therefore,wewillbegratefultoreadersforpointingtousanyneededcorrections.ThebookiswritteninawaythatwebelieveserveswellboththeusersofSystemVerilogassertionsinsimulationandalsothosewhopractice
