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ID:34474429
大小:165.25 KB
页数:10页
时间:2019-03-06
《an edge-endpoint-based configurable hardware architecture for vlsi cad layout design rule c》由会员上传分享,免费在线阅读,更多相关内容在教育资源-天天文库。
1、AnEdge-Endpoint-BasedConfigurableHardwareArchitectureforVLSICADLayoutDesignRuleCheckingZhenLuo,MargaretMartonosiandPranavAsharPrincetonUniversityandNECCCRL{zhenluo,mrm}@ee.princeton.edu,ashar@ccrl.nj.nec.comAbstractsetofchanges.PasthardwareDRCapproachesavoidedthisredesigncy
2、clebyacceleratingonlythebasicDesignrulechecking(DRC)isanimportantstepinVLSIdesignprimitivesofDRC,notthespecificrulechecks.TheinwhichthewidthsandspacingsofdesignfeaturesinaVLSIdrawbacktosuchapproachesisthattheyaccelerateonlyacircuitlayoutarecheckedagainstthedesignrulesofapor
3、tionoftheDRCanddonotadequatelyaddressthetrueparticularfabricationprocess.Inthepast,someeffortstobuildcomputebottlenecks.hardwareacceleratorsforDRChavebeenproposed,buttheseeffortswerehobbledbythefactthatitisoftenimpracticaltoOurproposalnotesthatwhiledesignrulesdochangeoverbu
4、ildadifferentrule-checkingASICeachtimedesignrulesorfabricationprocesseschange.timeandvarybetweenfabricationlines,theirfundamentalformremainssimilar.Thus,ourgoalistodesignaInthispaper,weproposeaconfigurablehardwareapproachtogeneral-purposeskeletonforDRCthatappliestonearlyDRC
5、.Becausetherule-checkingisbuiltinconfigurableallfabricationdesignrules,andthenalsototailorthehardware,itcangarnerimpressivespeedupsoversoftwarerule-checkinghardwareforaparticularfabricationapproaches,whileretainingtheflexibilityneededtoeasilyprocess.Tailoringtherule-checkst
6、oanindividualchangetherulecheckerasrulesorprocesseschange.Ourworkprocessallowsformuchbetterspeedupsandtakesproposesanedge-endpoints-basedmethodforperformingadvantageoftheinherentflexibilityofconfigurableManhattangeometrychecking;thisapproachisparticularlyhardware.Atthesamet
7、ime,thereconfigurationsarewell-suitedtotheconstraintsofconfigurablehardware.Althoughdesignrulesdochangeovertime,theirintrinsiclikelytobeinfrequentenough(every6-12months)thatsimilarityallowsustoproposeageneralscalablearchitecturetheFPGAreconfigurationtimeshaveessentiallynofo
8、rDRC.Wethendemonstrateourapproachbyapplyingthisimpactonperformance.architecturetoa
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