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1、IEICETRANS.,VOL.,NO.1SpecialIssueonVLSIDesignandCADAlgorithmAnEcientFPGATechnologyMappingTightlyCoupledwithLogicMinimizationyyyyKangYi,SeongYongOhm,andChuShikJhon,NonmembersSUMMARYTheFPGAlogicsynthesisconsistsoflogicmin-reducetheimplementationeortsfortech
2、nologymap-imizationstepandtechnologymappingstep.Thesetwostepsping.Thetechnologymappingsteptransformstheareusuallyperformedseparatelytoreducethecomplexityofthenetworksothateachnodecanbeimplementedbyanproblem.Conventionallogicminimizationmethodstrytomin-FPGAb
3、asicblock,whileminimizinggivenobjectives.imizethenumberofliteralsofagivenBooleannetwork,whileTheobjectivesoftechnologymappingareareaand/orFPGAtechnologymappingtechniquesattempttominimizethenumberofbasicblocks.However,minimizingthenumberofliter-delayofthelog
4、iccircuits.als,whichistargetarchitecture-independentfeature,doesnotal-TherearesomeexistingMUX-basedFPGAlogicwaysleadtominimizationofbasicblockcount,whichisaFPGAsynthesissystems:mis-pga(old)[2],mis-pga(new)architecturespecicfeature.Therefore,mostoftheexisti
5、ngtech-[3],Amap[4],proserpine[5],andTOS[6].Mis-nologymappingsystemstakeintoaccountreorganizationofitsinputcircuitstogetbettermappingresults.Suchalooselycou-pga(old)andmis-pga(new)performresynthesisusingpledlogicsynthesisparadigmmaycausedicultiesinndingthe
6、BDD(BinaryDecisionDiagram)orITE(If-Then-Else)optimalsolution.graphforeachnodethatcannotbeimplementeddi-Inthispaper,weproposeanewlogicsynthesisapproachrectlybyanFPGAbasicblock.Mis-pga(new)giveswherelogicminimizationandtechnologymappingstepsareper-aspecialize
7、dexactBooleanmatchingalgorithmforformedtightlycoupled.OursystemtakesintoaccountFPGAspecicfeaturesinlogicminimizationstepandthusourtech-ACT1FPGAandproducesthebestresultsamongex-nologymappingstepdoesnotneedtoresynthesizetheBooleanistingmethods.Amaprepresents
8、thewholeBooleannetwork.WeformulatethetechnologymappingproblemasanetworkasanITEdatastructureandperformsmap-graphcoveringproblem.Suchformulationprovidesmoreglobalpinginagreedyfashion.Itisveryfastbutdoesn