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1、FreescaleSemiconductorDocumentNumber:AN2910Rev.2,03/2007ApplicationNoteHardwareandLayoutDesignConsiderationsforDDR2SDRAMMemoryInterfacesbyDSDApplicationsFreescaleSemiconductor,Inc.Austin,TXThedesignguidelinespresentedinthisdocumentapplytoContents1Designer’
2、sChecklist...........................2productsthatleveragetheDDR2SDRAMIPcore,andthey2TerminationDissipation........................7arebasedonacompilationofinternalplatformsdesignedby3VREF......................................7FreescaleSemiconductor,Inc.Th
3、epurposeofthese4VTTVoltageRail.............................8guidelinesistominimizeboard-relatedissuesacross5LayoutGuidelinesfortheSignalGroups...........85.1Data—MDQ[0:63],MDQS[0:8],MDM[0:8],multiplememorytopologieswhileallowingmaximumMECC[0:7]............
4、......................9flexibilityfortheboarddesigner.5.2LayoutRecommendations...................96Simulation..................................12Becausenumerousmemorytopologiesandinterface7FurtherReading.............................12frequenciesarepossible
5、ontheDDR2SDRAMinterface,8RevisionHistory............................13Freescalehighlyrecommendsthatthesystem/boarddesignerverifyalldesignaspects(signalintegrity,electricaltimings,andsoon)throughsimulationbeforePCBfabrication.©FreescaleSemiconductor,Inc.,20
6、05,2007.Allrightsreserved.Designer’sChecklist1Designer’sChecklistInthefollowingchecklist,someoftheitemsarephrasedasquestion,othersasrequirements.Inallcases,werecommendthatyouconsiderthelineitemandcheckitoffintherightmostcolumnofTable1.Table1.DDR2Designer’s
7、ChecklistItemDescriptionYes/NoSimulation1.Haveoptimalterminationvalues,signaltopology,tracelengthsbeendeterminedthroughsimulationforeachsignalgroupinthememoryimplementation?Ifon-dieterminationisusedatboththememoriesandthecontroller,noadditionalterminationi
8、srequiredforthedatagroup.Fouruniquegroupingsexist:(1).DataGroup:MDQS(8:0),MDQS(8:0),MDM(8:0),MDQ(63:0),MECC(7:0)(2).Address/CMDGroup:MBA(2:0),MA(15:0),MRAS,MCAS,MWE.(3).ControlGroup:MCS(3:0),MCKE(3:0),MODT(3:
