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时间:2019-03-01
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1、OpenSource.OpenPossibilities.QuICConfidentialandProprietaryMultiplePerformanceMonitoringUnitsinPerfeventsPresentedby:AshwinChaugulePresentationDate:August19,2011PAGE1OpenSource.OpenPossibilities.Thatgravitydefyingdive!Photocred:DominatorFridayshttp://www.facebook.com/TheUltimatePagehttp://www
2、.facebook.com/photo.php?fbid=10150123348217273&set=pu.300060247272&type=1&theaterPAGE2OpenSource.OpenPossibilities.AgendaPerfeventsoverviewCurrenthardwarePMUsupportinperfeventsThemissingpartsWhereweareintheARMworldMultiplePMUsupportaddedinARMperfeventsWherewearenowWhat’scomingupinthene
3、arfuturePAGE3OpenSource.OpenPossibilities.OpenSource.OpenPossibilities.PerfeventsPAGE4PerfeventsFrameworkformonitoringthesystemSoftwareevents–Contextswitches,migrations,pagefaults…Hardwareevents–Cycles,instructions,cachestats…Andmuch,muchmore…UserspacesupportSys_perf_event_open(),IOCTL’
4、sEVENT_{DISABLE,ENABLE}/tools/perf/Structperf_event_attrperfbinaryincludesatonofsub-tools–perfstat–perfrecordreport–perftop–Newstuffaddedalmosteverymonth!PAGE5OpenSource.OpenPossibilities.OpenSource.OpenPossibilities.Perfevents:HardwarePMUsupportPAGE6CPUsidePMUsCPU0CPU1CPU2L1PM
5、UL1PMUL1PMUperfstatlsPrimarilysupportedonlyPerformancecounterstatsfor'ls':CPU-sidePMUs4938636cycles#1180.822M/secEasiertosupportusingper-1124192instructions#0.228IPC149797branches#35.816M/seccpudatastructures.51796branch-misses#34.577%Easiertosamplepertask/cache-references6、ounted>cache-missesperthread/perCPU0.005561630secondstimeelapsedPAGE7OpenSource.OpenPossibilities.MultiplePMUsButtherearemoreoftheseCPU0CPU1CPU2L1PMUL1PMUL1PMUL2CCL2PMUPAGE8OpenSource.OpenPossibilities.MultiplePMUsAndthensomemoreCPU0CPU1CPU2L1PMUL1PMUL1PMUL2CCL2PMUFabric1Fabric2Fabric3Fabri7、c4PAGE9OpenSource.OpenPossibilities.OpenSource.OpenPossibilities.CurrentStateofPerfeventsinARMPAGE10ARMPerfeventsCurrentlysupportingARMv6,v6mpv7–CortexA8,–CortexA9v11,v11mpxscale,xscalempCortexA15patchesinRFCstageAllabovesupportisforCP
6、ounted>cache-missesperthread/perCPU0.005561630secondstimeelapsedPAGE7OpenSource.OpenPossibilities.MultiplePMUsButtherearemoreoftheseCPU0CPU1CPU2L1PMUL1PMUL1PMUL2CCL2PMUPAGE8OpenSource.OpenPossibilities.MultiplePMUsAndthensomemoreCPU0CPU1CPU2L1PMUL1PMUL1PMUL2CCL2PMUFabric1Fabric2Fabric3Fabri
7、c4PAGE9OpenSource.OpenPossibilities.OpenSource.OpenPossibilities.CurrentStateofPerfeventsinARMPAGE10ARMPerfeventsCurrentlysupportingARMv6,v6mpv7–CortexA8,–CortexA9v11,v11mpxscale,xscalempCortexA15patchesinRFCstageAllabovesupportisforCP
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