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时间:2020-08-28
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1、1DigitalLogicDesignandApplicationLecture#10CombinationalLogicDesignPracticesDocumentationStandardandCircuitTimingUESTC,Spring20132Chapter6CombinationalLogicDesignPracticesHowtoconceiveacomplexsystem?––structuredthinkingSomeusefulcombinationalcomponents36.1DocumentationS
2、tandardAdocumentationpackagecontainthefollowingitems:Specification:descriptionofinterfaceandfunctionBlockdiagram:system’smajorfunctionmoduleandtheirbasicinterconnectionsSchematicdiagram(P360Figure6-17)Timingdiagram(P363Figure6-19)StructuredlogicdevicedescriptionCircuitdes
3、cription:explainshowthecircuitworksinternally4schematicdiagram51.BlockDiagramsAblockdiagramshowstheinputs,outputs,functionalmodules,internaldatapaths,andimportantcontrolsignalsofasystem.P345Figure6-162.GateSymbols7EquivalentGateSymbolsundertheGeneralizedDemorgan’sTheorem
4、inverterbufferANDNANDNORORORNORNANDAND83.ActiveLevelsactivelevelactivehighandactivelowasserted:asignalisatitsactivelevelnegated/deasserted:signalisnotatitsactivelevelsignalnameActivelevelsforpinsLogicFunctionsareperformedinsidethesymbolicoutlines.READYREQUESTGOREADY_LREQU
5、EST_LGO_LIndicateanActive-LowPin与门和或门的输入为1才能确保其输出9Example:activelevelsABFSignalactivestate:switch—off,lamp—lightABF000010100111Switch:1-offLamp:1-lightABFSwitch:0-offLamp:0-lightABF000011101111ABFF=A+B=(A’·B’)’AND:theoutputisassertedifandonlyifallitsinputsareasserted.Posi
6、tiveLogic1:HighLevel0:LowLevelActiveHighActiveLow10Example:activelevelsABFActivestate:switch—off,lamp—lightAND:theoutputisassertedifandonlyifallitsinputsareasserted.ABFABFInversionbubbleactive-lowpinnormalgatesNonnormalgatsLogicFunctionsareperformedinsidethesymbolicout
7、lines.115.Bubble-to-BubbleLogicDesignP353bubble-to-bubblelogicdesignrules127.DrawingLayoutflatschematicstructure13Hierarchicalschematicstructure14timingdiagramGOREADYDATtDATtDATGOREADYDATtRDYtRDYCausalityandPropagationDelay6.2CircuitTiming15GOREADYDATGOREADYDATtRDYmintRDY
8、maxMinimumandmaximumdelays6.2CircuitTiming166.2CircuitTimingpropagationdelayTiminganalysis:worst
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