FPGA流水线设计

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1、DesignofVeryDeepPipelinedMultipliersforFPGAsAlexPanato,SandroSilva,FlávioWagner,MarceloJohann,RicardoReis,SergioBampiUniversidadeFederaldoRioGrandedoSul-InstitutodeInformáticaAvBentoGonçalves,9500,BlocoIV,PortoAlegre,RS,Brazile-mail:

2、,johann,reis,bampi>@inf.ufrgs.brAbstractInthisworkweinvestigateamethodologytodesignthedeepestpipelinedcircuitsinFPGAs,startingfromVHDL.FPGAdeviceshavesomespecificcharacteristicsthatThisworkinvestigatestheuseofverydeeppipelinesforallowthedesignertoimplemen

3、ta"gatelevel"pipelineimplementingcircuitsinFPGAs,whereeachpipelinewithoptimalperformance,theonlyremarkbeingthatthestageislimitedtoasingleFPGAlogicelement(LE).Thewordgateheremeansany4-inputfunctionwithasinglearchitectureandVHDLdesignofaparameterizedinteger

4、output.LongerstageswillpresenttwicethedelayoflogicarraymultiplierispresentedandalsoanIEEE754elementsandwilluseanoutsideconnection.Shortercompliant32-bitfloating-pointmultiplier.WeshowhowtostagesdonottakeadvantageofthefactthattheFPGAcellwriteVHDLcellsthati

5、mplementsuchapproach,andhowcanimplementanyfunctionwiththesamedelay.Theideathearraymultiplierarchitecturewasadapted.SynthesisalreadyappearsinanAlteraApplicationBrief[3],butweandsimulationwereperformedforAlteraApex20KEdidnotfinddescriptionsandresultsofameth

6、odologyordevices,althoughtheVHDLcodeshouldbeportabletoimplementationanywhereelse.otherdevices.Forthisfamily,a16bitintegermultiplierDespitethefactthatFPGAarchitecturesdifferfromachievesafrequencyof266MHz,whilethefloatingpointvendortovendor,theystillpresent

7、asetofbasiccommonunitreaches235MHz,performing235MFLOPSinanfeaturesthatallowbuildinggatelevelpipelinesinVHDL.FPGA.Additionalcellsareinsertedtosynchronizedata,Bydoingso,itispossibletoreuseandmapthedesigntowhatimposessignificantareapenalties.Thisandothermany

8、differentdevices,andreuseitatthepressofaconsiderationstoapplythetechniqueinrealdesignsarebutton,incontrasttothefullcustomapproachalsoaddressed.Asacasestudy,wedevelopedanarchitectureforintegermultiplicationthatexploi