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1、《EDA技术》实验内容1.简单组合逻辑C=/(A+B)2.简单组合逻辑D=C·(A+B)3.简单组合逻辑D=C⊕A·B4.简单组合逻辑D=(/C+A)·(B⊕C)5.1位二进制加法器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYadd1_vISPORT(A:INSTD_LOGIC;B:INSTD_LOGIC;Cin:INSTD_LOGIC;Co:OUTSTD_LOGIC;S:OUTSTD_LOGIC);ENDadd1_v;ARCHITECTUREstructureOFadd1_vISBEG
2、INS<=AXORBXORCin;Co<=(AXORB)ANDCinOR(AANDB);ENDstructure;6.2位二进制加法器7.4位二进制加法器8.6位二进制加法器9.8位二进制加法器10.12位二进制加法器11.16位二进制加法器12.2选1开关13.3选1开关14.4选1开关LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux4ISPORT(input:INSTD_LOGIC_VECTOR(3DOWNTO0);sel:INSTD_LOGIC_VECTOR(1DOWNTO0);
3、y:OUTSTD_LOGIC);ENDmux4;ARCHITECTURErtlOFmux4ISBEGINPROCESS(input,sel)BEGINIF(sel=“00”)THENy<=input(0);ELSIF(sel=“01”)THENy<=input(1);ELSIF(sel=“10”)THENy<=input(2);ELSEy<=input(3);ENDIF;ENDPROCESS;ENDrtl;1.6选1开关2.8选1开关3.1-2数据选择器2选1数据选择器ENTTITYmux2ISPORT(d0,d1:INBIT;se
4、l:INBIT;s:OUTBIT);ENDmux2;ARCHITECTUREdataflowOFmux2ISSIGNALsig:BIT;--信号定义语句(内部信号,无方向)BEGINSig<=(d0ANDsel)OR(NOTselANDd1);S<=sig;--功能描述语句ENDdataflow;1.1-3数据选择器2.1-4数据选择器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux4ISPORT(d0:INSTD_LOGIC_VECTOR(7DOWNTO1);d1:INSTD_LOG
5、IC_VECTOR(7DOWNTO1);d2:INSTD_LOGIC_VECTOR(7DOWNTO1);d3:INSTD_LOGIC_VECTOR(7DOWNTO1);s0:INSTD_LOGIC;s1:INSTD_LOGIC;y:OUTSTD_LOGIC_VECTOR(7DOWNTO1));ENDmux4;ARCHITECTUREbehaveOFmux4ISBEGINlable:PROCESS(d0,d1,d2,d3,s0,s1)VARIABLEtmp:INTEGER;BEGINtmp:=0;IF(s0=‘1’)THENtmp:=
6、tmp+1;ENDIF;IF(s1=‘1’)THENtmp:=tmp+2;ENDIF;CASEtmpISWHEN0=>y<=d0;WHEN1=>y<=d1;WHEN2=>y<=d2;WHEN3=>y<=d3;WHENOTHERS=>NULL;--为了满足CASE语句全部选择项,空语句ENDCASE;ENDPROCESS;ENDbehave;1.1-5数据选择器2.1-8数据选择器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux8_v2ISPORT(A:INSTD_LOGIC_VECTO
7、R(2DOWNTO0);D0,D1,D2,D3,D4,D5,D6,D7:INSTD_LOGIC;G:INSTD_LOGIC;Y:OUTSTD_LOGIC;YB:OUTSTD_LOGIC);ENDmux8_v2;ARCHITECTUREdataflowOFmux8_v2ISBEGINPROCESS(A,D0,D1,D2,D3,D4,D5,D6,D7,G)BEGINIF(G='1')THENY<='0';YB<='1';ELSIF(G='0'ANDA="000")THENY<=D0;YB<=NOTD0;ELSIF(G='0'ANDA="
8、001")THENY<=D1;YB<=NOTD1;ELSIF(G='0'ANDA="010")THENY<=D2;YB<=NOTD2;ELSIF(G='0'ANDA="011")THENY<=D3;YB<=NOTD3;ELSIF(G=