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ID:9101530
大小:85.00 KB
页数:5页
时间:2018-04-17
《用vhdl在quartusii实现与或非》由会员上传分享,免费在线阅读,更多相关内容在应用文档-天天文库。
1、与门Libraryieee;Useieee.std_logic_1164.all;EntityanisPort(d1,d2:instd_logic;op:outstd_logic);Endan;Architecturem1ofanisBeginop<='1'when(d1='1'andd2='1')else'0';Endm1;或门Libraryieee;Useieee.std_logic_1164.all;EntityoorisPort(d1,d2:instd_logic;op:outstd_logic);Endoo
2、r;Architecturem1ofoorisBeginop<='0'when(d1='0'andd2='0')else'1';Endm1;非门Libraryieee;Useieee.std_logic_1164.all;EntityntisPort(d1:instd_logic;op:outstd_logic);Endnt;Architecturem1ofntisBeginop<='0'when(d1='1')else'1';Endm1;
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