tutorial_quartusii_intro_vhdl英文

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1、Quartus®IIIntroductionforVHDLUsersThistutorialpresentsanintroductiontotheQuartus®IIsoftware.ItgivesageneraloverviewofatypicalCADflowfordesigningcircuitsthatareimplementedbyusingFPGAdevices,andshowshowthisflowisrealizedintheQuartus®IIsoftware.Thedesignprocessisillus

2、tratedbygivingstep-by-stepinstructionsforusingtheQuartus®IIsoftwaretoimplementasimplecircuitinanAltera®FPGAdevice.TheQuartus®IIsystemincludesfullsupportforallofthepopularmethodsofenteringadescriptionofthedesiredcircuitintoaCADsystem.ThistutorialmakesuseoftheVHDLd

3、esignentrymethod,inwhichtheuserspecifiesthedesiredcircuitintheVHDLhardwaredescriptionlanguage.AnotherversionofthistutorialisavailablethatusesVeriloghardwaredescriptionlanguage.ThescreencapturesinthetutorialwereobtainedusingQuartus®IIversion8.1;ifotherversionsofthe

4、soft-wareareused,someoftheimagesmaybeslightlydifferent.Contents:GettingStartedStartingaNewProjectDesignEntryUsingVHDLCodeCompilingtheVHDLCodeUsingtheRTLViewerSpecifyingTimingContraintsQuartus®IIWindowsComputerAidedDesign(CAD)softwaremakesiteasytoimplementadesired

5、logiccircuitbyusingapro-grammablelogicdevice,suchasafield-programmablegatearray(FPGA)chip.AtypicalFPGACADflowisillustratedinFigure1.DesignEntrySynthesisFunctionalSimulationNoDesigncorrect?YesFittingTimingAnalysisandSimulationNoTimingrequirementsmet?YesProgrammingan

6、dConfigurationFigure1:TypicalCADflow.Itinvolvesthefollowingbasicsteps:•DesignEntry–thedesiredcircuitisspecifiedeitherbyusingahardwaredescriptionlanguage,suchasVerilogorVHDL,orbymeansofaschematicdiagram•Synthesis–theCADSynthesistoolsynthesizesthecircuitintoanetlistt

7、hatgivesthelogicelements(LEs)neededtorealizethecircuitandtheconnectionsbetweentheLEs•FunctionalSimulation–thesynthesizedcircuitistestedtoverifyitsfunctionalcorrectness;thesimulationdoesnottakeintoaccountanytimingissues•Fitting–theCADFittertooldeterminestheplaceme

8、ntoftheLEsdefinedinthenetlistintotheLEsinanactualFPGAchip;italsochoosesroutingwiresinthechiptomaketherequiredconnectionsbetweenspecificLEs•TimingAnalysis–propaga