EDA考试卷

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L2O世9年z主出现甚统仿真和合委普和征任E2技^，大口、>且便/计者脱里i鼎4于与，田正编^w源口这Hr卷丝为关元2r工，匕王且，是全•程还有5:土部更。内容或根据箫丁匕需八nj-出形力5.INPUT1INPUT0jrnjnjnjnjnJTTiJTJTnastaleMACHINE$0S0XS1Xs2)S3JsOXs1X6Xsi
“OP0]REGB00016.LIBRARYieee;ᔁᒹUSEieee.std_logic_1164.ALL;USEieee.std_logic_arith.ALL;USEieee.std_logic_unsigned.ALL;ENTITYram8IS--ram_8ḄPORT!⊤A:INstd_logic;din:INstd_logic_vector(7DOWNTO0);8#$ᐭ!dout:OUTstdZlogicZvector(7DOWNTO0);adr_8:INOUTItcflogic-vectorc?DOWNTO0));8#'ᔣ!ENDram8:7.)*᪗,᪾.Ḅᑁ0LIBRARYieee;USEieee.std_logic_l164.all;ENTITYiLcaseISPORT123(a,b,c,d:INStd_Logic;sei:INStd_Logic_Vector(1downto0);y,z:OUTStd.Logic);ENDiflcase;4567⊤ARCHITECTURElogicOFifBEGINif_label:PROCESS(a,b,c,d,sei)BEGINIFsel=,,OOMTHENy<=a;ELSIFsel=nO1MTHENy<=b;ELSIFsel=nl0MTHENy<=c;ELSEy<=d;ENDIF;ENDPROCESSifjabel;8.᥅9:᝱<.=ᐸ$*?@AB:᝱CḄDᦪ=FGHᙠJKLMᑮᩭJPQ

1RSᓄ஺VஹX15ᑖZ[⚪3ᑖ]1.CPLD^CPLD@_ᩖḄabcdᘤfḄgᑏ஺2.ᙠijb^ᙠijabᱯឋZInSystemProgrammability,ISP@ᢣn◤⌕qᵨbᘤ=?◤⌕stuv

21)USEõ2)PACKAGEõ3)ENTITYõ4)ARCHITECTUREõ5)CONFIGURATIONõöஹb⚪20ᑖ([⚪10ᑖ)1.ᵨVHDL2ùbᑏ2#ú1#ḄÓÑᘤcomponentadder_l(ûᳮý᝞þ)port(x,y,cin:instd_logic;libraryieee;cout,sum:outstd_logic);useieee.std_logic_l164.all;endcomponent;ENTITYadder_2issignaltemp:std_logic;port(al,aO,bl,b0,ci:instd_logic;beginsl,s2,co:outstdÿogic);endul:adder_lportmap(al,aO,ci,temp,s1);adder_2;u2:adder_lportmap(bl,b0,temp,co,s2);architectureoneofadder_2isendone;2.ᵨCASE
ᑏ2-4ṹᘤLIBRARYieee;USEieee.stdlogic1164.ALL;ENTITYdecoder2_4ISPORT(Al,AO,Gl,G2A,G2B:INSTD_L0GIC;Y:OUTSTD_L0GIC_VECT0R(3DOWNTO0));ENDdecoder2_4;ARCHITECTUREfunOFdecoder2_4ISSIGNALindata:STD_LOGIC_VECTOR(1DOWNTO0);BEGINencoder:indata<=C&B&A;PROCESS(indata,Gl,G2A,G2B)

3BEGINWHENOTHERS=>Y<="XXXX";IF(Gl=VANDG2A='O'ANDENDCASE;G2B='O')THENELSECASEindataISY<=/?1111?/;WHEN??00?/=>Y<=//1110?/;ENDIF;WHENENDPROCESSencoder;WHEN"10"=>Y<="1011";ENDfun;WHEN,,ir=>Y<=,,onr/Aᓅᜩ▾⚪23.VHDLBCD᪀F.USEGHI.PACKAGEGHJ,ENTITYGHJARCHITECTUREGHJ?KCONFIGURATIONGHJ஺5.D᪀NḄPQRSTStructurePQஹDateFlowPQஹBehaviorProcessPQ஺6.YZ᪗\᪾^Ḅᑁ`LIBRARYieee;USEieee.std_logic_l164.all;ENTITYiLcaseISPORT(a,b,c,d:INStd_Logic;sei:INStd_Logic_Vector(1downto0);y,z:OUTStd_Logic);ENDif_case;ARCHITECTURElogicOFijcaseISBEGINab
ifLlabel:PROCESS(a,b,c,.BEGINcdef⊤

4IFsel="OO"THENy<=a;ELSIFsel="01"THENy<=b;ELSIFsel="10"THENy<=c;ELSEy<=d;ENDIF;ENDPROCESSiMabel;hஹij⚪20ᑖmn⚪5ᑖo2.ᙠqbrsᵯuvw^xyKᑈ◅|}᪵Ḅ?᝞஺jTᨵḄefᓄ`᧕Aᔠrsᵯu|xyᑈ◅Ḅ஺RTm1oḄḄ¡u¢£Ḅ¡¤ᓽefᓄ஺m2o¦ᵯum3oᦋṹRS3.¨©|ª«¬P®ᢈ°?²³´¨©µ⚪¶jTª«¬P®ᢈ°mBoundaryScanTesting,BSTo,¸⌕ᵨº³´qbrsᘤ»¼ᱏḄ®µ⚪஺¾¿®qᙠᘤ»ÀÁÂÃᣓÅÆÇᦪÉ஺ᘤ»Ḅª«¬PᓫᐗÇÌÍ£rsÎÏef?ᡈ|Ñᡈᘤ»᪶Órsef^ᣓÅᦪÉ஺ÔÕᐭḄ®ᦪÉ×ÕᙢÙᐭª«¬Pᓫᐗ?ᣓÅḄᦪÉ×ÕÙZÚᙠᘤ»᜜Ü⚜ÞḄDßaÕàá஺᪗âḄª«¬P®ã◤⌕å᪷efç?ᓽTDIm®ᦪÉ¡ᐭoஹTD0m®ᦪÉ¡ZoஹஹTRSTm®èé¡ᐭoTMSm®ëS⌱íoKTCKm®ï¡ᐭo?TRSTÇÌðᵯuñᡠᨵóᢝª«¬PḄ¼ᱏᑁÜrsKª«õaÕ®஺öᵨª«¬Pᢈ°ÇÌÔ¼ᱏஹᵯuñ÷øùúḄq®ឋ஺üஹýᓣÿᑴḄDᘤᳮ᝞ᑨᑡᔲᨵ┯᝞ᨵᑣᢣ┯ᡠᙠ᦮஺10ᑖlibraryieee;useieee.std_logic_1164.al1;

5entitydfflisprocess(clk)port(clk,d:instd_logic;beginQ:outstd_logic);ifelk'eventandclk=Tenddffl;thenQ<=d;endif;architectureoneofdfflisendprocess;beginendone:'ஹ)*30ᑖ⌕,-1.)*.ᨵᑜ0Ḅ12஺2.34Ḅ5678஺3.9:4;<=>஺?libraryieee;__________@AᐗCD__________________________useieee.stdlogic1164.all;FᵨieeeDH_______________________ENTITYmux21is@AIJ______________________________port
a,b,s:inbit;a,b,sKLᐭNOᦪQRSbity:outbit;endmux21a;architectureoneofmux21is@AT᪀Jbeginy<=awhens='O'elseb;_____VS=0Wy=a,ᔲᑣXb________________________endone;;<=>-Y⌱?ᦪQ⌱[ᘤY

6Libraryieee;Useieee.std_logic_l164.all;Useieee.std_logic_unsigned.all;Entityup_downis@AIJ________________Port(clk,rst,en,up:instd_logic;Sum:outstd_logic_vector(2downto0);_______L᪗];<^ᔣ`___________Cout:outstd_logic);End;Architectureaofup_downisSignalcount:std_logic_vector(2downto0);@Aa.c_____________________________BeginProcess(clk,rst)_________defacelk,rst___________________________BeginIfrst=,O,thenCount<=(others=>5(T);_______ghij______________________________Elsifrising_edge(clk)then____᝞klᓣn__________________________________Ifen=Tthen_CaseupisWhenT=>count<=count+l;______________________________Whenothers=>count<=count-l;Vup=l,opqᦪEndcase;Endif;Endif;Endprocess;

7Sum<=count;Cout<='l'whenen=Tand((up=Tandcount=7)or(up=,0,andcount=0))else'O';d^acEnd;;<=>-?r3^s1/o1qᦪᘤ-VLᐭacUPXt1Wqᦪᘤs1VLᐭacUPXt0Wqᦪᘤo1஺uஹv⚪20ᑖx⚪10ᑖ1.vᑏᒹ{|ᑁ~ḄIJṹd:INstd_logic_vector(11NODK12^Lᐭ0DOWNTO0);NOOECLK1^Lᐭoe,elk:INstd_logic;NOADK12^ᔣ0ad:INOUTstd_logic_vector(11NOAK12^L0DOWNTO0);NOINT1^La:OUTstd_logic_vector(11NOAS?^LWᵨᑁDOWNTO0);✄int:OUTstd_logic;LIBRARYieee;as:BUFFERstd_logic);USEieee.std_logic_l164.ALL;ENDmy_design;ENTITYmy_designISPORT
2.ᑭᵨMAX+PLUSIIDHᐗᘤCDᘤ(c1)ᐗCᓄᡂ᝞ᡠ7Ḅᵯq஺

8LIBRARYieee;ENDCOMPONENT;USEieee.std_logic_J164.ALL;SIGNALd:std_logic_vector(4DOWNTOENTITYshifterIS0);PORT(din,elk:INstd_logic;BEGINdout:OUTd(0)<=din;stdogic);UO:dffPORTMAP(d(O),clk,d(l));ENDshifter;Ul:dffPORTMAP(d(l),clk,d(2));ARCHITECTUREaOFshifterISU2:dffPORTMAP(D=>d(2),clk=>COMPONENTdffclk,Q=>d(3));PORT(D,elk:INU3:dffPORTMAP(D=>d(3),clk=>std_logic;clk,Q=>d(4));Q-dout<=d(4);OUTstd_logic);ENDa;ᓅᜩ▾⚪32.vᘤCᑖKPLDPAC஺4.FPGAᵫv;<ᙽCLBஹvᓫᐗI/Ovvᵯ?rSRAMT᪀Ḅ¡¢£¤ᓫᐗ¥ᡂ஺5.CPLDHḄ;<ᓫᐗᜧᓫᐗ〉ᔠ;@A°᦮r©«ᑜᑖK±r²©«-ᦪQᜐᳮ²©«ᑴ²©«஺1.9:ᵨᳮLᐭ´pqᵯḄµ¶·஺

9¸-MAX+PLUSUḄq¹ᒹºq⚗¼Ḅ½¾qḄLᐭஹqv¿ஹq᪥ÁÂÃ@Wᑖ᪆ஹᘤCv'rhÅ஺qLᐭ-|ÆᵨᳮLᐭஹHDL1ÇÈÉஹÊËLᐭXÌ´Í஺qv¿-ᐜ᪷Qq⌕,@v¿Ïᦪv¿Ðᶍ᝞ᘤCḄ⌱[ஹ;<Òᔠ´ÍḄ⌱[X஺ᯠÔ᪷Q@ḄÏᦪÐᶍÕq⚗¼dÖ×⊤ÙÚஹ;<ÒᔠᘤC〉¡ÛÜÝÞᦻCஹàWaáᦻCÊvᦻCâᑖ᪆ÂÃvFᵨ஺q᪥Á⚗¼ÂÃ-ᒹº=>ÂÃஹWÂÃ@Wᑖ᪆|ᑭᵨãCḄÂÃ=>ᩭÁåq⚗¼Ḅ;<=>ᔲæç஺ᘤCvÁå-ᵨè¹ÂÃçéÔḄvᦻCê¹vᘤProgrammer°qëᑮI▭îᱏHᨬÔñòîᱏᙠ©«HḄI▭óÖឋ>஺ᙠq¹H᝞kõ┯ᑣ◤÷øùᑮqLᐭ▤ûᦋæ┯ᡈþ᦮ᵯÔ÷ÿ
஺2.INOUTBUFFERᨵ஺INOUT:ᔣBUFFER:ᔣᑁ✄஺ஹᑨ!"ᑡ$%ᔲᨵ┯(,᝞ᨵᑣᢣ┯(ᡠᙠ012᦮$$1:BEGINlibraryieee;PROCESS(SEL,a,b)useieee.std_logic_1164.all;IFsel='O'THENy<=aENTITYmux21isELSEy<=bport(a,b,seiinstd*ogic;Endify:outstd_logic)Endprocess;endmux21EndONEarchitectureoneofmux21is

10$2beginsignalA,EN:std_logic;ifEN=lthenB:=A;process(A,EN)endif;variableB:std_logic;endprocess;MஹNO$(30ᑖ)⌕T4.NOWᨵ"ᑜYḄ[\஺5.^_$Ḅ`ᳮbcd஺3._$efgh஺Libraryieee;klᐗnoUseieee.stdlogic_1164.all;Useieee.std_logic_unsigned.allEntityupdownisxy_________________________Port(elk,rst,en,up:instdlogic;Sum:outstd_logic_vector(2downto0);Cout:outstdlogic);Endupdown;Architectureaofup_downis᪀ySignalcount:stdlogicvector(2downto0);BeginProcess(elk,rst)0delkrstBeginIfrst=,O'thenCount<=(others=>J0,);Elsifrisingedge(clk)thenᓣ

11Ifen=,thenᦪᑴEN=1______________________CaseupisWhenT=>countீ=count+l;UP=1ᦪWhenothers=>countீ=countT;UP=0ᦪEndcase;Endif;Endif;Endprocess;Sum<=count;Cout<=,1'whenen='1,and((up='1'andcount=7)or(up='O'andcount=0))elseO;d________________________Enda;0ᦪḄᑴ⌮ᦪᘤ¢ஹ£$(20ᑖ)1.¤¥ᵯ§`ᳮb᝞"0¨ᵨVHDL[£ᑏᐸ$libraryieee;y:outbit);useieee.std_logic_1164.all;endmux21;ENTITYmux21isport(a,b,s:inbit;architectureoneofmux21is

12singled,e:bit;e<=bands;beginy<=dore;d<=aand(not)s;endone;2.ᵨᐗn°ᓄ[\²᝞bᡠ³ᵯ§஺ᐗn2ᐭµ¶·஺U1LIBRARYieee;std_logic);USEieee.stdJogic_1164.ALL;ENDCOMPONENT;ENTITYyf4ISSIGNALX,Y:std*ogic;PORT(A,B,C,D:INstdjogic;Z:OUTBEGINstd*ogic);Ul:yf2PORTMAP(A,B,X);ENDyf4;U2:yf2PORTMAP(C,D,Y);ARCHITECTUREaOFyf4ISU3:yf2PORTMAP(Al=>X,COMPONENTyf2C1=>Z,Bl=>Y);PORT(A1,B1:INstd_logic;ENDa;Cl:OUTᓅᜩ▾⚪41.CPLDḄᑁ¸Y¸¹ºY»¸᪀,¼½¾¿ᐭஹÀÁḄÂÃ%ÄkFPGAḄᑁ¸YᑖźY»¸᪀,ᔜghᓫᐗÁḄÂÃÈk஺2.CPLDÉḄefᓫᐗ%ᜧᓫᐗ0〉ᔠefÍÎÏÎÏ;FPGAḄefᓫᐗ%Ðᓫᐗ,〉ᔠᦪÑÍÎÏÎÏ஺

133.᪷ÑᦪÓÎÏḄghkl0Ô᦮ÕÎÏᑜᑖÖÕ×ÎÏᦪÑᜐᳮÙÎÏᑴ×ÎÏ஺6.ᐗn°ᓄ[\ḄÚᵨÛܲ,ᵫᐗnÞᐗn°ᓄÖᑖßᡂ஺ஹá⚪20ᑖ(ã⚪5ᑖ)4.á
VHDL$᪀1)USEklä2)PACKAGEklä3)ENT1TYklä4)ARCHITECTUREklä5)CONFIGURATIONkläஹ¤¥⌱¾ᵯ§᝞b0ᑨ!"ᑡ$%ᔲᨵ┯(0᝞ᨵᑣᢣ┯(ᡠᙠ012᦮$஺(10ᑖ)libraryieee;useieee.std_logic_1164.all;ENTITYMAXisport(al,a2,a3,s0,sl:inbit;outy:outbit);

14endmax;architectureoneofmaxiscomponentmux21aport(a,b,s:inbit;y:outbit);endcomponent;signaltemp:bit;beginul:mux21aportmap(a2,a3,s0,temp)u2:mux21aportmap(al,temp,sl,outy)endone;MஹNO$(30ᑖ)⌕T6.NOWᨵ"ᑜYḄ[\஺7.^_$Ḅæç³½b஺8._$efgh஺$¾libraryieee;_______klo_____________________________useieee.std_logic_l164.all;ENTITYmux21is________klxy____________________________port(a,b,s:inbit;y:outbit);endmux21a;______________________________________architectureoneofmux21iskl᪀y

15beginy<=awhens='O'elseb;endone;$libraryieee;useieee.std_logic_l164.all;entitybijiaoislport(datl,dat2:instd_lo»ic_vector(3downto0);dat3,dat4:instd_Iogic_vector(3downto0);outl,out2:outstd_logic_vector(3downto0));endbijiao;architectureoneofbijiaoisfunctionmax(a,b:instdlogicvector)èᦪy0éᦪa,b,ᐭ0ᦪÑêÍreturnstd_logic_vectorisvariabletemp:std_logic_vector(3downto0)klëìbeginifa>6thentemp:=a;elsetemp:=b;endif;ஹreturntempíî(ïᳮ),ᓝ______________________________endmaxèᦪyñ.outF<=max(datl,dat2);òᵨèᦪmax()ÔóíîoutlPROCESS(indata,Gl,G2A,G2B)

16BEGINIF(G1=TANDG2A='0'ANDG2B='O')THENCASEindataISWHEN"00"=>Y<="1110";WHEN"01"=>Y<="1101";WHEN"10"=>Y<="1011";WHEN"H"=>Y<="0111";WHENOTHERS=>Y<="XXXX";ENDCASE;ELSEY<="1111";ENDIF;ENDPROCESSencoder;2.,COUNTER10hḄᓝᑴᦪᘤ஺ᦪᘤÃôClkᓣᨵᦔஹ------CLKDOUT[3..O]-------CL.RNCO----CIölibraryieee;CNT:=0;useieee.std_logic_l164.all;ELSIFentitycounter10isclk='l'andclk'eventthenport(clk,CLRN:instd_logic;ifcnt=9thendout:outintegerrange0to9);cnt:=0;endcounterlO;elsearchitecturebehavofcounter10IScnt:=cnt+l;beginendif;process(clk)endif;variableent:integerrange0to9;dout<=cnt;beginendprocess;IFCLRN='0'THENendbehav;ᓅᜩ▾⚪61.÷ø£ᘤnEDAᢈúû⌕ᒹýMᜧ⌕þ0ᑖÿᜧᘤஹஹஹ஺2.ᘤᑖPLDPAC஺3.CPLD⚗Ḅ!᪀,ᓽᵫḄ&▣ᑡ)*Ḅᡈ▣ᑡᩭ-ᡂ/0஺1FPGA2ᵨ45⊤LUT!᪀Ḅ!᪀஺4.FPGAᵫ78ᙽ:CLBஹ;<ᓫᐗ:I/O;

17ASICᭆiᱯk஺ஹXஹ.ஹmASIC
ApplicationSpecialIntegratedCircuitnopᵨqᡂᵯB1s7rstuvcwxXLyz᜜X|ᨵ☠ឋXᡂZ,cMAX+PLUSHḄtஹdeஹde᪥/•A-JL.■XiinI-/k-LL\\de᪥:⚗cᒹ]/0ஹ_*ᑖ᪆XᑭᵨḄ/0ᩭde⚗Ḅ78/0ᔲ஺ᘤ&cᵨḄᦻpᘤ:Programmerdeᑮ▭ᱏXᨬᱏᙠḄ▭¡Pឋ0஺ᙠdeX᝞¢£¤┯¦Xᑣ◤L©ªᑮde«ᐭ▤®Xᦋ┯¦ᡈ°᦮ᵯBL²u஺5.³WHEN_ELSEᩩµ¶·¸[IF_ELSE^_[Ḅ¹º஺»cWHEN_ELSEᩩµ¶·¸[¼᪗kX¾ᨵᨬᨵᑖ¶¿ÀÁᡂo£¤;`P[XÀÁÃᙠ!᪀w஺IF_ELSE^_[ᨵᑖ¶¿^_[XÀÁÃᙠÄ஺?ஹᑨÆᑡ_ᔲᨵ┯¦X᝞ᨵᑣᢣ£┯¦ᡠᙠX`aD_EunÉḄw!᪀w஺:10ᑖ
10ᑖ_1:c:outinteger);libraryieee;endsample;useieee.std_logic_l164.all;architectureoneofsampleisENTITYsampleisbeginport(a,b:ininteger;c<=a+b;

18endone;process(A,EN)_2cbeginENTITYsample1isifEN='l'thenB<=A;port(a,en:instd_logic;endif;b:outstd_logic);endprocess;endsample1;endone;architectureoneofsample1isíஹîï_(3begin஺ᑖ)⌕çc9.îïòᨵᑜôḄ[஺10.ö£÷_Ḅøᳮúû¶஺11.üý÷_78/0஺12.ᦋᵨWITH_SELECT_WHENᑏᑡ஺Libraryieee;Useieee.stdlogic_1164.a]];'(ᐗ*+entityqk_11isport(a,b,c,d,en:instd_logic;s:instd_logic_vector(1downto0);7ᐭ9:s;<=Ḅ7ᐭ?@op:outstdlogic);endqk_ll;architecturear_lofqkllissignalf:stdlogicvector(2downto0);beginf<=en&s;H7ᐭ9:enIsJKLMNf

19process(f)OP9:fḄQᓄHSTUprocessbegincasefiswhen"100"=>opீ=a;whenYY10rY=>op<=b;whenYY110//=>op<=c;whenothers=>op<=d;ᐸ\]^YH7ᐭ_:dLMNopendcase;endprocess;endar_l;I
QK_11olI-r`...........abcd;efᨵhdienḄj⌱lᦪn⌱oᘤ஺ᵨWITH_SELECT_WHENᑏrsarchitecturear_lofqk_l1isesignalf:stdlogicvector(2Libraryieee;downto0);Useieee.std_logic_l164.al1;beginentityqk11isf<=en&s;port(a,b,c,d,en:instd_logic;withfselects:instd_logic_vector(1downtoop<=awhen"100",0);bwhen"101",op:outstd_logic);cwhen"110",endqk_ll;dwhenothers;

20endar_l;tஹv20ᑖx2.ᐹᨵz{iḄ4=|Uᑴ~ᦪᘤ᝞ᡠYᵨVHDLᑏᐸCZT4-----CLKQ[3..O]—ebeginlibraryieee;process(clr,clk)useieee.std_logic_l164.all;beginuseieee.std_logic_unsigned.all;ifclr='l'thenq<="0000";entitycnt4iselsif(clk'eventandclk='l')thenport(clk:instd_logic;q<=q+lclr:instd_logic;endif;q:bufferstd_logic_vector(3downto0));endprocess;endcnt4;endbehav;architecturebehavofcnt4is2.ᵨᐗ*ᓄ~᝞ᡠᵯ஺ᐗ*27ᐭ஺LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYyf4IS

21PORT(A,B,C,D:INstdogic;Z:OUTstdjogic);ENDyf4;ARCHITECTUREaOFyf4ISCOMPONENTyf2PORT(A1,B1eINstd_logic;Cl:OUTstdjogic);ENDCOMPONENT;SIGNALX,Y:std_logic;BEGINUl:yf2PORTMAP(A,B,X);U2:yf2PORTMAP(C,D,Y);U3:yf2PORTMAP(Al=>X,C1=>Z,Bl=>Y);ENDa;ᓅᜩ▾⚪71.ᑭᵨEDAᢈUᵯ~~7ᐭᨵY᝞e7ᐭஹᳮ7ᐭஹᦻ7ᐭ஺3.᪷nᦪ¡Ḅcd'(Y¢H᦮¤¡ᑜᑖ<¤¦¡eᦪnᜐᳮ¨¡I©ᑴ¦¡஺5.ª᪀¬Ḅª᪀ᓄs®⌕sᵯḄ°ᡂYᓽᐗ*³´ḄµJ஺®⌕ᵨᐗ*ᓄI¶ᡂᩭ¸¹஺

226.VHDLḄº»¼ᨵjYᓽab½¾¼ஹᐵ½¾¼ஹ¾½¾¼ஹÀÁ½¾¼஺7.VHDLᦻ®⌕ᒹÃᦪMÄᦻI᪗Ƽ஺ÇஹÈÉ⚪20ᑖvË⚪5ᑖx6.ÈsPROCESSª᪀ḄÇÌᑖ᪀ᡂYÀÍÎUஹÏI9:³´Ḅᐵ஺ÉePROCESSª᪀;ᵫÇÌᑖ᪀ᡂḄYᓽUÍÎÌᑖYÏsÌᑖIOP9:Ñᦪ⊤஺ᔜ¤U;À½ḄYÔᐜÖ³ᑖY×ØÙᙠª᪀¬ÛÏ;ᢥϽḄYᨵᐜÖ³ᑖY×ØÙᙠUÛ9:Ùᙠª᪀¬IU³´Y;ᵨÝÞᡂᔜ¤U³´ᦪnßᣚ஺7.ásEDAâ*¡ᒹãäåæᙽ஺Ée~7ᐭ¦æᙽY~ᦪn+¦æᙽYᑖ᪆éê¦æᙽYëᔠíî¦æᙽYïðï@¦æᙽñ஺4.ÈsWITH_SELECT_WHEN⌱o9:LMICASE_WHENÏḄòó஺:WITH_SELECT_WHEN⌱o9:LMÛ;⌹:YᨬÖ;ᑖ:;ÀY×ØÙᙠª᪀¬Û஺CASE_WHENÏÛ;ᑖ:;ÏY×ØÙᙠUÛ஺Çஹᑨ÷ᑡ;ᔲᨵ┯úY᝞ᨵᑣᢣý┯úᡠᙠv10ᑖxeUSEIEEE.STD_LOGIC_UNSIGNED.ALL;LIBRARYIEEE;ENTITYzytl2ISUSEEEE.STD_LOGIC_1164.ALL;PORT(R,EN,CP:INSTD_LOGIC;USEEEE.STD_LOGIC_ARITH.ALL;Q:BUFFER

23STD_LOGIC_VECTOR(3DOWNTO0);ELSIF(CP'EVENTANDCP=T)THENCO:OUTSTD_LOGIC);IFEN='O'THENENDzytl2;Q<=QGARCHITECTUREclOOFzytl2isELSIFQ="1011"THENBEGINQ<=“0000”;CO<='1'WHEN(EN=TANDQ="10H")ELSEELSEQ<=Q+1;'O';ENDIF;PROCESS(R,CP)ENDIF;BEGINENDPROCESS;IFR=TTHENENDc10;Q<="0000";jஹþÿ
(30ᑖ)⌕13.ᨵᑜḄ஺14.
Ḅᳮ஺15.
!஺
1y:outstd_logic_vector(7downtoLibraryieee;Useieee.stdlogical164.all;Useieee.std_logic_signed.all;89ᐗ;

24Libragieee;Usei^ee.std_logic_1164.all;89ᐗ;ientitycfd1isport(j^p,d:instd_logic;lnq:outstdlogic);nLq,nqend1;architectureoneofcfd1isbeginendpatch;process(cp)JKLcpMᓄOPQarchitectureoneofpatchisRSprocessbeginbeginprocess(d)JKLdMᓄOPQifcp'eventandcp='1'thenRSprocesspᓣrᑮᩭObeginq<=d;_______Ld[\]q_______y<=(notd)+1;PLdḄWX1nq<=notd;ḄYZ[\]yendif;endprocess;endprocess;endone;endone;PATCHCFD_1CPQDNQ^!_⊡ṹb*.........!_Dwxᘤᡂᵯe஺
2

25zஹ|
}20ᑖ~1.ᵨVHDL|ᑏXᘤᡈᘤ;Ḅ
᝞ᡠ:OR2AACO---BSO■2.Xᘤ
ᡈ
libraryieee;libraryieee;useieee.std_logic_l164.all;useieee.stdogic_l164.all;entityh_adderisentityor2aisport(a,b:instdogic;port(a,b:instd_logic;co,so:outstd_logic);c:outstdogic);endh_adder;endor2a;architectureoneofh_adderisarchitectureoneofor2aisbeginbeginso<=not(axor(notb));c<=aorb;co<=aandb;endone;endone;2.ᙠp⍝⚪ḄẠpᵨᐗ;ᓄ1ᐰXᘤ஺
libraryieee;

26useieee.std_logic_1164.all;port(a,b:instd_logic;entityadderisc:outstd_logic);port(ain,bin,cin:instd_logic;endcomponent;cout,sum:outstd_logic);signald,e,f:std_logic;endentityLadder;beginarchitecturefdlofLadderisul:h_adderportcomponenth_addermap(a=>ain,b=>bin,co=>d,so=>e);port(a,b:instd_logic;u2:h_adderportco,so:outstd_logic);map(a=>e,b=>cin,co=>f,so=>sum);endcomponent;u3:or2aportmap(d,f,cout);componentor2aendfd1;