最新基本数字逻辑单元的设计教学讲义ppt课件.ppt

《最新基本数字逻辑单元的设计教学讲义ppt课件.ppt》由会员上传分享，免费在线阅读，更多相关内容在教育资源-天天文库。

1、基本数字逻辑单元的设计4.1组合逻辑设计4.1.2三态缓冲器和总线缓冲器8bit单向总线缓冲器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYtri_buf8ISPORT(din：INSTD_LOGIC_VECTOR(7DOWNTO0);dout：OUTSTD_LOGIC_VECTOR(7DOWNTO0);en：INSTD_LOGIC);ENDtri_buf8;ARCHITECTUREdata_flowOFtri_buf8ISPROCESS(en,din)BEGINIF(en='1')THENdout<=din;ELSEdout<

2、="ZZZZZZZZ";ENDIF;ENDPROCESS;ENDdata_flow;Endin(0)din(1)din(2)din(3)din(4)din(5)din(6)din(7)dout(0)dout(1)dout(2)dout(3)dout(4)dout(5)dout(6)dout(7)BCD码—段选码译码器。BCD码输入与LED显示器字段的对应关系BCD码数字显示段hgfedcba00000110000000001111111001001021010010000113101100000100410011001010151001001001106100000100

3、11171010011110008100000001001910010000其它11111111BCD-段选码译码器d0d1d2d3abc.hgdefVccLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL；ENTITYseg_delISPORT(d：INSTD_LOGICVECTOR(3DOWNTO0);q：OUTBIT_VECTOR(7DOWNTO0));ENDseg_del;ARCHITECTUREseg_rtlOFseg_delISBEGINPROCESS(d)BEGINCASEdISWHEN"0000"=>q<="11000000";W

4、HEN"0001"=>q<="11111001";WHEN"0010"=>q<="10100100";WHEN"0011"=>q<="10110000";WHEN"0100"=>q<="10011001";WHEN"0101"=>q<="10010010";WHEN"0110"=>q<="10000010";WHEN"0111"=>q<="11011000";WHEN"1000"=>q<="10000000";WHEN"1001"=>q<="10010000";WHENOTHERS=>q<="11111111";ENDCASE;ENDPROCESS;ENDseg-rtl;

5、4.1.4运算器的设计一位全加器的设计.LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL；ENTITYfull_adderISPORT(a,b,ci：INSTD_LOGIC;sum,cout：OUTSTD_LOGIC);ENDfull_adder;ARCHITECTURErtlOFfull_adderISBEGINsum<=aXORbXORci；cout<=(aANDb)OR(aANDci)OR(bANDci)；ENDrtl;asumbcicout4位串行进位加法器ciabsumcociabsumcociabsumcociabsumcoS0S1

6、S2S3COCIA0B0A1B1A2B2A3B3SUMCIABSUMCIABSUMCIABSUMCIABCI0A0B0CI1A1B1CI2A2B2CIn-1An-1Bn-1进位产生逻辑S0S1S3Sn-1coutCIA[0:n-1]B[0:n-1]N位超前进位加法器超前进位加法器各位加法器产生进位的逻辑表达式为：定义为进位生成函数,定义为进位传递函数,则全加器的各位和为：4位超前进位加法器LIBRARYIEEE;USEIEEESTD_LOGIC_1164.ALL;ENTITYadder4ISPORT(a,b：INSTD_LOGIC_VECTOR(3DOWNTO0)ci：I

7、NSTD_LOGIC;sum：OUTSTD_LOGIC_VECTOR(3DOWNTO0);cout：OUTSTD_LOGIC);ENDadde4r；ARCHITECTURErtl_adder4OFadder4ISSIGNALg,p,c：STD_LOGIC_VECTOR(3DOWNTO0)；BEGINp(0)<=a(0)ORb(0);p(1)<=a(1)ORb(1);p(2)<=a(2)ORb(2);g(0)<=a(0)ANDb(0);a[3:0]b[3:0]ciSum[3:0]coutg(1)<=a(1)ANDb(1);g(2