基本数字逻辑单元的设计.ppt

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1、第四章基本数字逻辑单元的设计4.1组合逻辑设计4.1.2三态缓冲器和总线缓冲器8bit单向总线缓冲器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYtri_buf8ISPORT(din：INSTD_LOGIC_VECTOR(7DOWNTO0);dout：OUTSTD_LOGIC_VECTOR(7DOWNTO0);en：INSTD_LOGIC);ENDtri_buf8;ARCHITECTUREdata_flowOFtri_buf8ISPROCESS(en,din)BEGINIF(en='1')THENdout<=din;ELSEdout<=

2、"ZZZZZZZZ";ENDIF;ENDPROCESS;ENDdata_flow;Endin(0)din(1)din(2)din(3)din(4)din(5)din(6)din(7)dout(0)dout(1)dout(2)dout(3)dout(4)dout(5)dout(6)dout(7)双向总线缓冲器用VHDL语言描述的双向总线缓冲器。endir功能1X高阻态00a<=b01b<=aadirenbLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYdobl_tri_buf8ISPORT(a,b：INOUTSTD_LOGIC_VECTOR

3、(7DOWNTO0);dir,en：INSTD_LOGIC);ENDdobl_tri_buf8；ARCHITECTURErtlOFdobl_tri_buf8ISSIGNALaout,bout：STD_LOGIC_VECTOR(7DOWNTO0);BEGINP1:PROCESS(a,dir,en)BEGINIF((en='0')AND(dir='1'))THENbout<=a;ELSEbout<="ZZZZZZZZ";ENDIF;b<=bout;ENDPROCESSP1;P2:PROCESS(b,dir,en)BEGINIF((en='0')AND(dir='0'))THENaou

4、t<=b;ELSEaout<="ZZZZZZZZ";ENDIFa<=aout;ENDPROCESSP2;ENDrtl;BCD码—段选码译码器。BCD码输入与LED显示器字段的对应关系BCD码数字显示段hgfedcba0000011000000000111111100100102101001000011310110000010041001100101015100100100110610000010011171010011110008100000001001910010000其它11111111BCD-段选码译码器d0d1d2d3abc.hgdefVccLIBRARYIEEE;USE

5、IEEE.STD_LOGIC_1164.ALL；ENTITYseg_delISPORT(d：INSTD_LOGICVECTOR(3DOWNTO0);q：OUTBIT_VECTOR(7DOWNTO0));ENDseg_del;ARCHITECTUREseg_rtlOFseg_delISBEGINPROCESS(d)BEGINCASEdISWHEN"0000"=>q<="11000000";WHEN"0001"=>q<="11111001";WHEN"0010"=>q<="10100100";WHEN"0011"=>q<="10110000";WHEN"0100"=>q<="1001

6、1001";WHEN"0101"=>q<="10010010";WHEN"0110"=>q<="10000010";WHEN"0111"=>q<="11011000";WHEN"1000"=>q<="10000000";WHEN"1001"=>q<="10010000";WHENOTHERS=>q<="11111111";ENDCASE;ENDPROCESS;ENDseg-rtl;4.1.4运算器的设计一位全加器的设计.LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL；ENTITYfull_adderISPORT(a,b,ci：INSTD_LOGIC;

7、sum,cout：OUTSTD_LOGIC);ENDfull_adder;ARCHITECTURErtlOFfull_adderISBEGINsum<=aXORbXORci；cout<=(aANDb)OR(aANDci)OR(bANDci)；ENDrtl;asumbcicout4位串行进位加法器ciabsumcociabsumcociabsumcociabsumcoS0S1S2S3COCIA0B0A1B1A2B2A3B3SUMCIABSUMCIABSUMCIABSUMCIABCI