数字集成电路课件.ppt

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1、DigitalIntegratedCircuitsADesignPerspectiveSemiconductorMemoriesJanM.RabaeyAnanthaChandrakasanBorivojeNikolicDecember20,2002ChapterOverviewMemoryClassificationMemoryArchitecturesTheMemoryCorePeripheryReliabilityCaseStudiesSemiconductorMemoryClassificationRead-WriteMemoryNon-VolatileRead-WriteMemor

2、yRead-OnlyMemoryEPROME2PROMFLASHRandomAccessNon-RandomAccessSRAMDRAMMask-ProgrammedProgrammable(PROM)FIFOShiftRegisterCAMLIFOMemoryTiming:DefinitionsMemoryArchitecture:DecodersWord0Word1Word2WordN22WordN21StoragecellMbitsMbitsNwordsS0S1S2SN22A0A1AK21K5log2NSN21Word0Word1Word2WordN22WordN21Storagece

3、llS0Input-Output(Mbits)IntuitivearchitectureforNxMmemoryToomanyselectsignals:Nwords==NselectsignalsK=log2NDecoderreducesthenumberofselectsignalsInput-Output(Mbits)DecoderArray-StructuredMemoryArchitectureProblem:ASPECTRATIOorHEIGHT>>WIDTHAmplifyswingtorail-to-railamplitudeSelectsappropriatewordHier

4、archicalMemoryArchitectureAdvantages:1.Shorterwireswithinblocks2.Blockaddressactivatesonly1block=>powersavingsBlockDiagramof4MbitSRAMSubglobalrowdecoderGlobalrowdecoderSubglobalrowdecoderBlock30Block31128KArrayBlock0Block1ClockgeneratorCS,WEbufferI/ObufferY-addressbufferX-addressbufferx1/x4controll

5、erZ-addressbufferX-addressbufferPredecoderandblockselectorBitlineloadTransfergateColumndecoderSenseamplifierandwritedriverLocalrowdecoder[Hirose90]Contents-AddressableMemoryAddressDecoderI/OBuffersCommands29ValidityBitsPriorityEncoderAddressDecoderI/OBuffersCommands29ValidityBitsPriorityEncoderMemo

6、ryTiming:ApproachesDRAMTimingMultiplexedAdressingSRAMTimingSelf-timedRead-OnlyMemoryCellsWLBLWLBL1WLBLWLBLWLBL0VDDWLBLGNDDiodeROMMOSROM1MOSROM2MOSORROMWL[0]VDDBL[0]WL[1]WL[2]WL[3]VbiasBL[1]Pull-downloadsBL[2]BL[3]VDDMOSNORROMWL[0]GNDBL[0]WL[1]WL[2]WL[3]VDDBL[1]Pull-updevicesBL[2]BL[3]GNDMOSNORROMLa

7、youtProgrammmingusingtheActiveLayerOnlyPolysiliconMetal1DiffusionMetal1onDiffusionCell(9.5lx7l)MOSNORROMLayoutPolysiliconMetal1DiffusionMetal1onDiffusionCell(11lx7l)ProgrammmingusingtheContactLayerOnlyMOSNA