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1、第二章CPLD/FPGA使用方法AHDL语言AHDL实验设计可编程逻辑器件的选择CPLD,FPGAorASIC?容量宏单元数，逻辑单元数寄存器数，门数存储器大小速度Tpd可用管脚数固定输入管脚，可定义输入/输出管脚工作电压电源电压接口电压功耗封装形式配置方式一次编程OTP(OneTimeProgrammable)可再编程(Re-Programmable)保持型，ISP上电加载型，需要外置EPROMSelectionofCPLDorFPGAIfcircuithavingalotofcombinatoriallog
2、ic,useCPLDIfcircuithavingalotofRegisterlogic,useFPGA100%combinatoriallogic0%Register0%combinatoriallogic100%RegisterCPLDFPGAcont...SelectCPLDorFPGAdependsonthecircuitapplicationCPLDforCombinatorialLogic>RegisterLogicFPGAforRegisterLogic>CombinatorialLogicGat
3、ecountneedCPLDgatecountissmallerthanFPGASpeedGradeCPLDhavinglesspintopinI/OdelayCPLDingeneralrunfasterthanFPGAMemoryneedFPGAsupportMemoryPriceingeneralFPGAislowerincostthanCPLDSelectGuideMAX7000SFamilyMembersFeatureUsablegatesMacrocellsMaxUserI/OtPD(ns)fcnt(
4、MHz)7032/S60032365178.67064/S1,25064686151.570961,80096766151.57128/S2,5001281007.51257160/S3,2001601047.51257192/S3,750192124101007256/S5,00025616410100FLEX10KFamilyMembersFeature10K1010K2010K3010K4010K5010K10010K70Typicalgates10,00020,00030,00040,00050,000
5、100,00070,000Logicelements5761,1521,7282,3042,8804,9923,744TotalRAMbits6,14412,28812,28816,38420,48024,57618,432TotalRegisters7201,3441,9682,5763,1845,3924,096MaxUserI/O150198248278310406358AvailableNowNowNowNowNowNowNowMulti-voltSystemGuidelineBothCPLDandFP
6、GAfromAlterasupportMulti-voltsysteminterfaceCouplesuggestionwhendoingMulit-voltdesign5Vdevice,use70000S/10K/6K/8KA/9K3.3Vdevice,use7000A/10KA/10KV/6KA/9KA2.5Vdevice,use7000B/10KEcont...VCCINTGNDINTCoreVCCIOGNDIOVCCIOGNDIOUserOption: AllowsInterface to5.0-,3.
7、3-& 2.5-VSystemsVCCIOBasedonProcess: UserConnects toPowerSupplyVCCINTcont...5.0-VDeviceswithMultiVoltInterface(1)InputofDeviceDrivenbyAlteraDeviceOutputMustHave5.0-VTolerance.(2)InputofDeviceDrivenbyAlteraDeviceOutputMustHave3.3-VTolerance.(3)UseOpen-drainou
8、tputswithpull-upto5.0V.ApplicableDevices:FLEX10K,FLEX6000,FLEX8000,MAX7000/S,MAX9000/AüüüüüüüüüüüüüNote:Forsomeofthesmallerpackages,therearenoVCCIOpins,andthereforedoesnotsupportMulti-voltinterf
