数字钟实验论文.pdf

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1、数字钟的设计小组成员及学号：黄婷婷15352135黄淑桦15352134黄蕊15352132院系：数据科学与计算机学院专业：移动信息工程专业班级：1506摘要本设计为一个多功能的数字钟，具有时、分、秒计数显示功能，以24小时循环计数；具有校时功能。拓展实现有秒表功能，整点报时功能，倒计时功能。本设计以硬件描述语言Verilog为系统逻辑描述手段设计文件，利用Vivado进行编译仿真，由各个基本模块共同构建了一个基于FPGA的数字钟。本实验主要经编译和仿真所设计的程序，可通过实验输出的波形图和FPGA板

2、子的具体操作进行验证。关键词：数字时钟，硬件描述语言，Verilog，FPGAAbstractThedesignforamulti-functionaldigitalclock,withhours,minutesandsecondscountdisplaytoa24-hourcyclecount;withschoolfunctionsDevelopingstopwatchfunction,thewholepointtimekeepingfunction,countdownfunction.Thisde

3、signusesthehardwaredescriptionlanguageVerilogasthesystemlogicdescriptionmethodtodesignthedocument,usesVivadotocarryonthecompilationsimulation,byeachbasicmodulealtogetherconstructedaFPGAbaseddigitalclock.ThisexperimentismainlycompiledandSimulationofthede

4、signprocess,throughtheexperimentaloutputwaveformandFPGAboardspecificoperationstoverify.Keywords：digitalclock,hardwaredescriptionlanguage,Verilog,FPGA目录摘要....................................................................................................

5、..2Abstract................................................................................................3选题背景.............................................................................................6一，课题研究的必要性.....................................

6、.......................6二，课题研究的内容................................................................6三，实验可行性.........................................................................7四，设计理念....................................................................

7、.........9五，编程及仿真软件Vivado.....................................................9六，实验流程...........................................................................10数字化时钟系统软件设计方案.......................................................10一，整体设计方案描述...........

8、...............................................10二，模块描述...........................................................................10系统调试...........................................................................................24