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1、第五讲常用组合、时序逻辑电路的VHDL描述译码器与编码器设计数码转换电路设计比较器设计数据选择器设计只读存储器设计三态与双向接口设计算术逻辑单元(ALU)设计七段LED显示译码器设计先进先出(FIFO)缓冲器设计键盘扫描及抖动消除电路设计状态机设计编码器编码器常常运用于影音压缩或通信方面。编码器压缩数据传输线或网络译码器解压缩数据原来需要传送2N位数据量,现在只用N位X7X6X5X4X3X2X1X0Y2Y1Y0000000010000000001000100000100010000010000110001000010000100000101010000
2、00110100000001118—3编码器真值表LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYCoderISPORT(X:INSTD_LOGIC_VECTOR(7DOWNTO0);EN:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(2DOWNTO0));ENDCoder;ARCHITECTUREaOFCoderISSIGNALSel:STD_LOGIC_VECTOR(8DOWNTO0);BEGINSel<=EN&X;--将EN、X7、X6、…X0合并以简化程序WITHSelSELECT
3、Y<="000"WHEN"100000001","001"WHEN"100000010","010"WHEN"100000100","011"WHEN"100001000","100"WHEN"100010000","101"WHEN"100100000","110"WHEN"101000000","111"WHEN"110000000","000"WHENOTHERS;ENDa;Sel(8)<=EN;Sel(7)<=X(7);Sel(6)<=X(6);Sel(5)<=X(5);Sel(4)<=X(4);Sel(3)<=X(3);Sel(2)<=X(2
4、);Sel(1)<=X(1);Sel(0)<=X(0);仿真结果编码器根据真值表,利用With…Select语句或Case…When语句或When…Else语句来设计——查表法根据逻辑函数式,使用并行直接赋值语句实现。(真值表——卡诺图化简——逻辑运算符)译码器译码器除了在影音压缩或通信方面用于解码外,还可以用作显示译码(将4位BCD码转换成7段码输出,以便在7段LED显示器上显示),另外,还经常被应用在地址总线进行地址选址的工作和芯片的选通控制。A2A1A0Y7Y6Y5Y4Y3Y2Y1Y00000000000100100000010010000001
5、0001100001000100000100001010010000011001000000111100000003—8译码器真值表LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYencoderISPORT(A:INSTD_LOGIC_VECTOR(2DOWNTO0);EN:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDencoder;ARCHITECTUREaOFencoderISSIGNALsel:STD_LOGIC_VECTOR(3DOWNTO0);BEG
6、INsel<=A&EN;WITHselSELECTY<="00000001"WHEN"0001","00000010"WHEN"0011","00000100"WHEN"0101","00001000"WHEN"0111","00010000"WHEN"1001","00100000"WHEN"1011","01000000"WHEN"1101","10000000"WHEN"1111",“11111111”WHENOTHERS;--“XXXXXXXX"ENDa;存储器地址译码器设计EEPROMSRAMPeripheralPeripheralPROMS
7、hadowFFFFC0008000401040084000LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYdecodeISPORT(address:INSTD_LOGIC_VECTOR(15Downto0);Valid,boot_up:INSTD_LOGIC;Sram,prom,eeprom,shadow,Periph1,periph2:OUTSTD_LOGIC);ENDdecode;ARCHITECTUREmem_decodeOFdecodeISBeginMapper:Process(address,vali
8、d,boot_up)beginshadow<=‘0’;prom<=‘0’;periph1<=‘