EDA数字时钟设计.doc

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1、Quartus数字时钟设计一.设计功能1.可以快速设置时钟起始值；2.在59分50秒时开始报时，七声低音，一声高音，报完刚好整点。二.功能实现1.顶层设计（采用BDF文件图形设计，文件名：timer.bdf）2.秒计时器模块设计libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitysecond1isport(clk1s:instd_logic;reset:instd_logic

2、;sec2,sec1:bufferstd_logic_vector(3downto0);--秒的十位和个位seco:outstd_logic);--秒计时器的进位输出end;architectureAofsecond1isbeginprocess(clk1s,reset)beginifreset='0'thensec2<="0000";sec1<="0000";--清零秒计时器seco<='0';elsifclk1s'eventandclk1s='1'thenif(sec1="1001"andsec2="0101")thense

3、c2<="0000";sec1<="0000";--在59秒时回零seco<='1';--进位elsif(sec1="1001")thensec1<="0000";sec2<=sec2+1;seco<='0';elsesec1<=sec1+1;seco<='0';endif;endif;endprocess;end;3.分计时器模块设计libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;

4、entityminute1isport(clkm,clk1s,setm:instd_logic;--秒进位输入，1HZ校分时钟输入信号，校分控制信号min2,min1:bufferstd_logic_vector(3downto0);--分计时器的十位和个位minco:outstd_logic);end;architectureAofminute1issignalclkx:std_logic;beginPclkm:process(clkm,clk1s,setm)begin--根据是否校分选择计时时钟ifsetm='1'thenc

5、lkx<=clk1s;--利用clk1s信号对分的初值进行快速设置elseclkx<=clkm;--利用秒的进位信号正常计时endif;endprocess;Pcontm:process(clkx)beginifclkx'eventandclkx='1'thenif(min1="1001"andmin2="0101")thenmin1<="0000";min2<="0000";minco<='1';--59分时回零并进位elsif(min1="1001")thenmin1<="0000";min2<=min2+1;minco<=

6、'0';elsemin1<=min1+1;minco<='0';endif;endif;endprocess;end;4.时计时器模块设计libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityhour1isport(clkh,clk1s,seth:instd_logic;hou2,hou1:bufferstd_logic_vector(3downto0));--时的十位和个位e

7、nd;architectureAofhour1issignalclky:std_logic;beginPclkh:process(clkh,clk1s,seth)Begin--根据是否校时选择计时时钟ifseth='1'thenclky<=clk1s;--利用clk1s信号对时的初值进行快速设置elseclky<=clkh;--利用分的进位信号正常计时endif;endprocess;Pconth:process(clky)beginifclky'eventandclky='1'thenif(hou1="0011"andhou2

8、="0010")thenhou1<="0000";hou2<="0000";--23时回零elsif(hou1="1001")thenhou1<="0000";hou2<=hou2+1;elsehou1<=hou1+1;endif;endif;endproces