静态时序分析(基于quartus2)

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1、时序分析原理：需要对器件布线中的每一条路径进行与时序设置/需求相关的分析（比门级仿真和板级测试更方便快捷）不过这种时序分析事先需要设计者输入时序要求和时序例外（这个需求用來指求布线器的palcement&nnning."J以将这个输入需求Launch&LatchEdgesDATA―XDataValidXLatchEdgeLaunchEdge:theedgewhich“launches"thedatafromsourceregisterLatchEdge:theedgewhichlatches"thedataat

2、destinationregister(withrespecttothelaunchedge,selectedbytiminganalyzer:typically1cycle)Setup&HoldDATAPRErcUQ>CLRCLKCLK•suThDATAXValidXSetup:TheminimumtimedatasignalmustbestableBEFOREclockedgeHold:TheminimumtimedatasignalmustbestableAFTERclockedgeTogether,t

3、hesetuptimeandholdtimeformaDataRequiredWindow,thetimearoundaclockedgeinwhichdatamustbestable.DataArrivalTime■ThetimefordatatoarriveatdestinationregistersDinputDataArrivalTime=launchedge+Tclk1+Tco+TdataClockArrivalTime■Thetimeforclocktoarriveatdestinationregi

4、ster'sclockinputClockArrivalTime=latchedge+Tcl<2DataRequiredTime・Setup■TheminimumtimerequiredforthedatatogetlatchedintothedestinationregisterDataRequiredTime=ClockArrivalTime-TSL1・SetupUncertaintyDataRequiredTime■HoldTheminimumtimerequiredforthedatatogetlatc

5、hedintothedestinationDataRequiredTime=ClockArrivalTime+Th+HoldUncertaintySetupSlack■Themarginbywhichthesetuptimingrequirementismet.Itensureslauncheddataarrivesintimetomeetthelatchingrequirement.从上图可以看出，止的setupslack代表时序得到满足，而负的setupslack则是时序没有得到满足的表现。HoldSlac

6、k■Themarginbywhichtheholdtimingrequirementismet.Itensureslatchdataisnotcorruptedbydatafromanotherlaunchedge.CLKREG1.CLKREG1.QREG2.DREG2.CLK同样从以上的时序图可以看出,正的holdslack代表吋序得到满足，而负的holdslack时序则不满足时序。