静态时序分析基本原理和时序分析模型

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1、Quartus®IISoftwareDesignSeries:TimingAnalysis-Timinganalysisbasics2ObjectivesDisplayacompleteunderstandingoftiminganalysis3Howdoestimingverificationwork?Everydevicepathindesignmustbeanalyzedwithrespecttotimingspecifications/requirementsCatchtiming-relatederrorsfasterandeasierthangate-levelsimul

2、ation&boardtestingDesignermustentertimingrequirements&exceptionsUsedtoguidefitterduringplacement&routingUsedtocompareagainstactualresultsINCLKOUTDQCLRPREDQCLRPREcombinationaldelaysCLR4TimingAnalysisBasicsLaunchvs.latchedgesSetup&holdtimesData&clockarrivaltimeDatarequiredtimeSetup&holdslackan

3、alysisI/OanalysisRecovery&removalTimingmodels5Path&AnalysisTypesThreetypesofPaths:ClockPathsDataPathAsynchronousPaths*ClockPathsAsyncPathDataPathAsyncPathDQCLRPREDQCLRPRETwotypesofAnalysis:Synchronous–clock&datapathsAsynchronous*–clock&asyncpaths*Asynchronousreferstosignalsfeedingtheasynchronou

4、scontrolportsoftheregisters6Launch&LatchEdgesCLKLaunchEdgeLatchEdgeDataValidDATALaunchEdge:theedgewhich“launches”thedatafromsourceregisterLatchEdge:theedgewhich“latches”thedataatdestinationregister(withrespecttothelaunchedge,selectedbytiminganalyzer;typically1cycle)7Setup&HoldSetup:Theminimumti

5、medatasignalmustbestableBEFOREclockedgeHold:TheminimumtimedatasignalmustbestableAFTERclockedgeDQCLRPRECLKThValidDATATsuCLKDATATogether,thesetuptimeandholdtimeformaDataRequiredWindow,thetimearoundaclockedgeinwhichdatamustbestable.8DataArrivalTimeDataArrivalTime=launchedge+Tclk1+Tco+TdataCLKREG1.

6、CLKTclk1DataValidREG2.DTdataLaunchEdgeDataValidREG1.QTcoThetimefordatatoarriveatdestinationregister’sDinputREG1PREDQCLRREG2PREDQCLRComb.LogicTclk1TCOTdata9ClockArrivalTimeClockArrivalTime=latchedge+Tclk2CLKREG2.CLKTclk2LatchEdgeThetimeforclocktoarriveatdestinationregister’sclockinputREG1PREDQCL

7、RREG2PREDQCLRComb.LogicTclk210DataRequiredTime-SetupDataRequiredTime=ClockArrivalTime-Tsu-SetupUncertaintyCLKREG2.CLKTclk2LatchEdgeTheminimumtimerequiredforthedatatogetlatchedintothedestinationregisterTsuDataValidREG2.DDatamustbev