静态时序分析总结

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1、StaticTimingAnalyzerUsingPrimeTimeDec232007Presentedbyzhaoicdesign_zhao@126.com2013-3-191AgendaFBasicFlow¢AdvancedAnalysis¢Summary¢Example2013-3-192STAinstruction¢Statictiminganalysisconcept¾Verifiestiming(setup,hold…)¾Isexhaustive¾Usesformal,mathematicaltechniquesinst

2、eadofvectors¾Doesnotusedynamiclogicsimulation¢STA:Easier,fasterdebuggingofyourdesigntiming2013-3-193ComprehensiveTimingChecks¢Manytypesoftiminganddesignrulechecks¾TimingcheckscanbedelaycalculatedorSDFannotated¾Setupandholdcheck¾DesignrulechecksconsistentwithDC,PC,Astro

3、2013-3-194BasicTimingAnalysisFlowUsingPrimeTime¢SetupDesignEnvironment¾Searchpath,linkpath¾Readdesigns,libraries,thenlink¾Readsdfandsetoperationcondition,environmentsetting¢SpecifyTimingAssertions¾Clockperiod/waveform/uncertainty/latency¾Input/outputdelays¢SpecifyTimin

4、gExceptions¾Multi-cyclepathsandFalsepaths¾Min/maxdelays,segmentation,disabledarcs¢PerformAnalysis,CreateReports¾Checktiming¾Timingreportsandconstraintreports¾Bottleneckandcoverageanalysisreports2013-3-195SetUpEnvironment¢Definitionssearch_path:specifieswheretosearchfor

5、designandlibrarydatalink_path:specifieswhichdesignandlibrarydatatobeloadedduringlinking(link_design)link_design:commandresolvesalldesignreferences¢Example:pt_shell>setsearch_path“../syn/lib”pt_shell>setlink_path“*stdcell.db.IO.dbmemory.db”pt_shell>read_verilog$project_

6、dir/top.vpt_shell>current_designtoppt_shell>link_designpt_shell>read_sdf-typesdf_max$sdf_dir/top.sdf¢Designtip1.ThesetupisdifferentwithDCsetup2.Beforenewdesignwasload,removedolddesignandconstraint3.report_annotated_delay:Reportbackannotateddelays4.report_annotated_chec

7、k:Reportbackannotatedtimingchecks2013-3-196Operatingconditionanddesignenvironment¢Settingtheoperatingconditions,wire-loadmodels,input/outputenvironment¢Examplept_shell>set_operating_conditions-librarypt_lib-analysis_typeon_chip_variationworstpt_shell>set_wire_load_mod

8、eenclose(pregate)pt_shell>set_wire_load_modelstd_100k_w(pregate)pt_shell>remove_wire_load_model(postgate)pt_shell>set