基于Altera Quartus II的模块化设计

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1、基于AlteraQuartusII的模块化设计应用        和ISE不一样，QuartusII代码的模块化视图并不是你把子模块例化到顶层模块以后就能马上在工程代码窗口看到一个清晰的层次图。而是必须在你编译后才能够看到层次化的视图。        我在这里列举一个串口通信（实验10）的实例：       编写完该HDL的代码，还没有编译，此时在ProjectNavigator窗口中只有顶层模块my_uart_top。       顶层模块如下（详细的注释代码请参考相关实验）：///////////////////

2、/////////////////////////////////////////////////////////////modulemy_uart_top(                            clk,rst_n,                            rs232_rx,rs232_tx                            );inputclk;inputrst_n;inputrs232_rx;outputrs232_tx; wirebps_start1,bps_

3、start2;wireclk_bps1,clk_bps2;wire[7:0]rx_data;wirerx_int;  ////////////////////////////////////////////speed_select        speed_rx(                                                     .clk(clk),                                                                  

4、                                                     .rst_n(rst_n),                                                 .bps_start(bps_start1),                                                 .clk_bps(clk_bps1)                                          ); my_uart_rx

5、                 my_uart_rx(                                                        .clk(clk),                                                                                                                       .rst_n(rst_n),                                  

6、               .rs232_rx(rs232_rx),                                                 .rx_data(rx_data),                                                 .rx_int(rx_int),                                                 .clk_bps(clk_bps1),                          

7、                       .bps_start(bps_start1)                                          ); ///////////////////////////////////////////                                        speed_select        speed_tx(                                                     .clk(c

8、lk),                                                 .rst_n(rst_n),                                                 .bps_start(bps_start2),